H01S5/309

VERTICAL CAVITY SURFACE EMITTING LASER, METHOD FOR FABRICATING VERTICAL CAVITY SURFACE EMITTING LASER

A vertical cavity surface emitting laser includes: a supporting base having a principal surface including III-V compound semiconductor containing gallium and arsenic as constituent elements; and a post disposed on the principal surface. The post has a lower spacer region including a III-V compound semiconductor containing gallium and arsenic as group-III elements, and an active layer having a quantum well structure disposed on the lower spacer region. The quantum well structure has a concentration of carbon in a range of 210.sup.16 cm.sup.3 or more to 510.sup.16 cm.sup.3 or less. The quantum well structure includes a well layer and a barrier layer. The well layer includes a III-V compound semiconductor containing indium as a group-III element, and the barrier layer includes a III-V compound semiconductor containing indium and aluminum as group-III elements. The lower spacer region is disposed between the supporting base and the active layer.

Consumer semiconductor laser

A vertical cavity surface emitting laser device includes a substrate, a first-type doped distributed Bragg reflector (DBR) disposed on the substrate, a first electrode disposed on the substrate, an active layer disposed on the first-type doped DBR, a second-type DBR disposed on the active layer, and a second electrode disposed on the second-type DBR. The second-type DBR defines a first doping concentration region, and a second doping concentration region disposed between the first doping concentration region and the active layer and that has a doping concentration less than that of the first doping concentration region. The second-type doped DBR has a confinement member formed in the first doping concentration region, and defining an aperture.

Component having a multiple quantum well structure

The invention relates to a component (10) having a semiconductor layer sequence, which has a p-conducting semiconductor layer (1), an n-conducting semiconductor layer (2), and an active zone (3) arranged between the p-conducting semiconductor layer and the n-conducting semiconductor layer, wherein the active zone has a multiple quantum well structure, which, from the p-conducting semiconductor layer to the n-conducting semiconductor layer, has a plurality of p-side barrier layers (32p) having intermediate quantum well layers (31) and a plurality of n-side barrier layers (32n) having intermediate quantum layers (31). Recesses (4) having flanks are formed in the semiconductor layer sequence on the part of the p-conducting semiconductor layer, wherein the quantum well layers and/or the n- and p-side barrier layers extend in a manner conforming to the flanks of the recesses at least in regions. The interior barrier layers have a larger average layer thickness than the p-side barrier layers.

Semiconductor optical device
10236663 · 2019-03-19 · ·

A semiconductor optical device includes a laminated structure constituted of a first compound semiconductor layer of an n type, an active layer, and a second compound semiconductor layer of a p type, the active layer including at least 3 barrier layers and well layers interposed among the barrier layers, and the semiconductor optical device satisfying Eg.sub.p-BR>Eg.sub.n-BR>Eg.sub.Well when a bandgap energy of the barrier layer adjacent to the second compound semiconductor layer is represented by Eg.sub.p-BR, a bandgap energy of the barrier layer between the well layers is represented by Eg.sub.Well, and a bandgap energy of the barrier layer adjacent to the first compound semiconductor layer is represented by Eg.sub.n-BR.

Quantum cascade laser device

A quantum cascade laser device includes a semiconductor substrate, an active layer provided on the semiconductor substrate, and an upper clad layer provided on a side of the active layer opposite to the semiconductor substrate side and having a doping concentration of impurities of less than 1?10.sup.17 cm.sup.?3. Unit laminates included in the active layer each include a first emission upper level, a second emission upper level, and at least one emission lower level in their subband level structure. The active layer is configured to generate light having a center wavelength of 10 ?m or more due to electron transition between at least two levels of the first emission upper level, the second emission upper level, and the at least one emission lower level in the light emission layer in each of the unit laminates.

Semiconductor Light Source

A semiconductor light source is disclosed. In one embodiment, a semiconductor light source includes at least one semiconductor laser for generating a primary radiation and at least one conversion element for generating a longer-wave visible secondary radiation from the primary radiation, wherein the conversion element for generating the secondary radiation comprises a semiconductor layer sequence having one or more quantum well layers, and wherein, in operation, the primary radiation is irradiated into the semiconductor layer sequence perpendicular to a growth direction thereof, with a tolerance of at most 15.

Integrated circuit implementing a VCSEL array or VCSEL device

A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800 C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Q.sub.p for an intermediate p-type layer relative to built-in electron charge Q.sub.n for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).

Integrated Circuit Implementing a VCSEL Array or VCSEL Device
20180241173 · 2018-08-23 · ·

A semiconductor device includes an array of VCSEL devices with an annealed oxygen implant region (annealed at a temperature greater than 800 C.) that surrounds and extends laterally between the VCSEL devices. A common anode and a common cathode can be electrically coupled to the VCSEL devices, with the common anode overlying the annealed oxygen implant region. The annealed oxygen implant region can funnel current into active optical regions of the VCSEL devices and provide current isolation between the VCSEL devices while avoiding an isolation etch between VCSEL devices. In another embodiment, a semiconductor device includes an annealed oxygen implant region surrounding a VCSEL device. The VCSEL device(s) can be formed from a multi-junction layer structure where built-in hole charge Q.sub.p for an intermediate p-type layer relative to built-in electron charge Q.sub.n for a bottom n-type layer is configured for diode-like current-voltage characteristics of the VCSEL device(s).

Optoelectronic integrated circuit

A semiconductor device includes an n-type ohmic contact layer, cathode and anode electrodes, p-type and n-type modulation doped quantum well (QW) structures, and first and second ion implant regions. The anode electrode is formed on the first ion implant region that contacts the p-type modulation doped QW structure and the cathode electrode is formed by patterning the first and second ion implant regions and the n-type ohmic contact layer. The semiconductor device is configured to operate as at least one of a diode laser and a diode detector. As the diode laser, the semiconductor device emits photons. As the diode detector, the semiconductor device receives an input optical light and generates a photocurrent.

Laser diode chip

A laser diode chip is described. In an embodiment the laser diode chip includes an n-type semiconductor region, a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region, wherein the active layer is in the form of a single quantum well structure. The single quantum well structure includes a quantum well layer, which is arranged between a first barrier layer and a second barrier layer, wherein the first barrier layer faces the n-type semiconductor region, and the second barrier layer faces the p-type semiconductor region. An electronic bandgap E.sub.QW of the quantum well layer is smaller than an electronic bandgap E.sub.B1 of the first barrier layer and smaller than an electronic bandgap E.sub.B2 of the second barrier layer, and the electronic bandgap E.sub.B1 of the first barrier layer is larger than the electronic bandgap E.sub.B2 of the second barrier layer.