Externally-strained devices such as LED and FET structures as discussed herein may have strain applied before or during their being coupled to a housing or packaging substrate. The packaging substrate may also be strained prior to receiving the structure. The strain on the devices enables modulation of light intensity, color, and electrical currents in some embodiments, and in alternate embodiments, enables a fixed strain to be induced and maintained in the structures.

A light-emitting device may comprise a set of layers comprising a substrate layer, and a set of epitaxial layers deposited on the substrate layer. The set of epitaxial layers may include a strained layer. The strained layer may include a set of active zones to be used to generate optical gain. The light-emitting device may comprise a set of trenches etched into a subset of the set of layers of the light-emitting device. The set of trenches may prevent a set of defects or dislocations in a wafer from which the light-emitting device was formed from propagating into the set of active zones.

An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.

An optical semiconductor device outputting a predetermined wavelength of laser light includes a quantum well active layer positioned between a p-type cladding layer and an n-type cladding layer in thickness direction. The optical semiconductor device includes a separate confinement heterostructure layer positioned between the quantum well active layer and the n-type cladding layer. The optical semiconductor device further includes an electric-field-distribution-control layer positioned between the separate confinement heterostructure layer and the n-type cladding layer and configured by at least two semiconductor layers having band gap energy greater than band gap energy of a barrier layer constituting the quantum well active layer. The optical semiconductor device is applied to a ridge-stripe type laser.

An optical device has a gallium and nitrogen containing substrate including a surface region and a strain control region, the strain control region being configured to maintain a quantum well region within a predetermined strain state. The device also has a plurality of quantum well regions overlying the strain control region.

A semiconductor laser diode (LD) having an optical grating is disclosed. The LD includes a lower cladding layer that buries the optical grating, an active layer, and an upper cladding layer. The active layer has a multi-quantum well (MQW) structure of barrier layers and well layers alternately arranged. The MQW structure further includes intermediate layers between the barrier layers and the well layers. The intermediate layers have a lattice constant between that of the barrier layers and that of the well layers. Each intermediate layer has a thickness thinner than 1 nm.

Externally-strained devices such as LED and FET structures as discussed herein may have strain applied before or during their being coupled to a housing or packaging substrate. The packaging substrate may also be strained prior to receiving the structure. The strain on the devices enables modulation of light intensity, color, and electrical currents in some embodiments, and in alternate embodiments, enables a fixed strain to be induced and maintained in the structures.

A light emitting element according to the present disclosure includes: a GaN substrate; a first strain correction layer disposed above the GaN substrate and including In.sub.xGa.sub.1-xN of a first conductivity type where x is greater than 0 and less than or equal to 1; a first low refractive index layer disposed above the first strain correction layer, including In.sub.1-a-bGa.sub.aAl.sub.bN of the first conductivity type, and having relationships of (a/0.98)+(b/0.8)1, (a/1.02)+(b/0.85)1, and (a/1.03)+(b/0.68)1; a first clad layer disposed above the first low refractive index layer, including Al.sub.zGa.sub.1-zN of the first conductivity type where z is greater than or equal to 0.03 and less than or equal to 0.06, and having a refractive index higher than a refractive index of the first low refractive index layer; and an active layer disposed above the first clad layer.

An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer, at least one stress balance layer and a die attachment layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein the at least one stress balance layer is made of at least one conductive material; the die attachment layer is formed on a bottom surface of the at least one stress balance layer, wherein the die attachment layer is made of conductive material. By locating the at least one stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.

An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.