A power converter and a corresponding method of converting power are presented. The power converter includes a ground port, an input port for receiving an input voltage and an output port for providing an output voltage; an inductor; a flying capacitor; a network of switches; and a driver to drive the network of switches with a sequence of states during a drive period. The sequence of states includes a first state and a second state. In the first state one of the input port and the output port is coupled to the ground port via a first path comprising the inductor. In the second state the remaining state among the input port and the output port is coupled to the ground port via a second path and a third path, the second path comprising the flying capacitor and bypassing the inductor, and the third path comprising the inductor.

A semiconductor device comprises: a voltage generator suitable to pump a power source voltage to generate a first pumping voltage in response to an operation clock, a clock generator suitable to generate the operation clock having a first frequency during an initial operation period in which a level of the first pumping voltage is at a first level and to generate the operation clock having a second frequency after the initial operation period, the second frequency generated to be lower than the first frequency in response to a rise in a level of the first pumping voltage to a second level greater than the first level, and an internal circuit suitable to perform a predetermined internal operation in response to the first pumping voltage.

A semiconductor device comprises: a voltage generator suitable to pump a power source voltage to generate a first pumping voltage in response to an operation clock, a clock generator suitable to generate the operation clock having a first frequency during an initial operation period in which a level of the first pumping voltage is at a first level and to generate the operation clock having a second frequency after the initial operation period, the second frequency generated to be lower than the first frequency in response to a rise in a level of the first pumping voltage to a second level greater than the first level, and an internal circuit suitable to perform a predetermined internal operation in response to the first pumping voltage.

An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.

An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.

A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) prefluxing the inductor then charging the capacitor causing an increased current to flow in the inductor and (2) prefluxing the inductor then discharging the capacitor causing increased current to flow in the inductor. The inductor prefluxing steps enable the circuit to provide increased output voltage and/or increased output current.

A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) prefluxing the inductor then charging the capacitor causing an increased current to flow in the inductor and (2) prefluxing the inductor then discharging the capacitor causing increased current to flow in the inductor. The inductor prefluxing steps enable the circuit to provide increased output voltage and/or increased output current.

A charge-pump control circuit includes an oscillator which supplies a clock for driving a charge pump driver to supply a first gate voltage to a discharging transistor in order to control discharge from a battery, and driving a charge pump driver to supply a second gate voltage to a charging transistor in order to control charge to the battery, respectively; and a drive control circuit which sets a control target voltage as one of the first gate voltage and the second gate voltage having a lower voltage in order to control generation of the clock by the oscillator according to the control target voltage.

A charge-pump control circuit includes an oscillator which supplies a clock for driving a charge pump driver to supply a first gate voltage to a discharging transistor in order to control discharge from a battery, and driving a charge pump driver to supply a second gate voltage to a charging transistor in order to control charge to the battery, respectively; and a drive control circuit which sets a control target voltage as one of the first gate voltage and the second gate voltage having a lower voltage in order to control generation of the clock by the oscillator according to the control target voltage.

A wireless power receiving device includes: a wireless power receiving coil, an AC-DC circuit, a capacitor buck circuit, and a battery, wherein the capacitor buck circuit includes at least two capacitors and a switch; an output terminal of the wireless power receiving coil is connected to an input terminal of the AC-DC circuit, and an output terminal of the AC-DC circuit is connected to an input terminal of the capacitor buck circuit, and an output terminal of the capacitor buck circuit is connected to the battery; in a case that the switch is in a first connection state, the at least two capacitors are in a series state and store energy; and in a case that the switch is in a second connection state, the at least two capacitors are in a parallel state and release energy.