A transformerless parallel active rectifier system includes N multiphase common mode inductors directly connected to a shared multiphase AC input with no intervening transformer, and N active rectifiers coupled to respective ones of the N multiphase common mode inductors and having respective DC outputs coupled to a shared DC bus, where N is an integer greater than 1. The N active rectifiers have ground current regulators and are synchronized to provide DPWM switching control signals synchronized to one another to regulate their respective ground currents and concurrently regulate the shared DC bus voltage.

A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.

Provided is a power supply apparatus that supplies power received from an external power supply to a load, the power supply apparatus comprising: a plurality of power supply circuitries, each of which has switching elements, that are allowed to supply power to the load separately; and a processor that controls a number of the power supply circuitries supplying power to the load according to a required power level of the load.

A power converter comprising an energy transfer element is coupled between an input of the power converter and an output of the power converter. A cascode circuit generates a first sense signal and a second sense signal. A controller controls the switching of the cascode circuit to transfer energy from the input of the power converter to the output of the power converter. The controller comprising a current sense circuit generates a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal. A control circuit generates a control signal in response to the current limit signal and the overcurrent signal. A drive circuit comprising a first stage gate drive circuit generates a drive signal in response to the control signal to reduce EMI, and a second stage of gate drive circuit to enable accurate current sensing of the cascode circuit.

A pre-charging circuit is provided, including a first switch, a second switch, a diode, a first current-limiting apparatus, a capacitor, and an inverter unit. One end of the pre-charging circuit is connected to a power grid. After the first current-limiting apparatus, the first switch, and the diode are connected in series, one end of a line formed by the series connection is connected to one terminal of the capacitor, the other end of the line is connected to a first-phase alternating current of the power grid, and the other terminal of the capacitor is connected to a second-phase alternating current of the power grid via the inverter unit and the second switch successively.

A controller of an embodiment includes a limiter receiving an active current command initial value, limiting a maximum value of the active current command initial value with a predetermined value, and outputting a first value; a circuit to calculate a reactive current command initial value; a calculator to calculate a reactive current command adjustment value; a unit receiving the first value as an input, and calculating a reactive current upper limit value such that a composite value of the first value and the reactive current upper limit value is equal to or smaller than an input current maximum value; and a limiter to output the reactive current command adjustment value or the reactive current upper limit value, whichever is smaller. The predetermined value is a value to set the reactive current upper limit value to a value larger than zero and smaller than the input current maximum value.

A voltage source inverter comprises a rectifier circuit having an input for connection to a multi-phase AC power source and converting the AC power to DC power and an inverter circuit for receiving DC power and converting the DC power to AC power. A DC bus circuit is connected between the rectifier circuit and the inverter circuit to provide a relatively fixed DC voltage for the inverter circuit, the DC bus circuit comprising a DC bus including a first bus rail comprising an inductor and a second bus rail, and a soft charge circuit connected in series with a DC bus capacitor network between the first and second rails, the DC bus capacitor network comprising a first capacitor branch including a pair of capacitors with a fuse connected in series between the capacitors, a balancing resistor across each capacitor and a snubbing capacitor connected across the fuse.

This application provides a converter and an on-board charger, to avoid a short-circuit fault of the converter while inhibiting a surge impact. The converter includes: a power factor correction PFC circuit, a surge protection circuit, and a switch circuit. The PFC circuit is configured to: convert a first component of a first alternating current received by an alternating current terminal of the PFC circuit into a first direct current, and output the first direct current through a direct current terminal of the PFC circuit; and convert a second direct current received by the direct current terminal of the PFC circuit into a second alternating current, and output the second alternating current through the alternating current terminal of the PFC circuit.

In a switching power supply device, a control circuit controls a first thyristor, a second thyristor, and a switching element according to an input voltage. The control circuit maintains the first thyristor in an on state while maintaining the second thyristor and the switching element in an off state in a first period in which the absolute amplitude value is equal to or less than a first threshold value within the latter half of a first half-cycle of the input voltage at startup, and maintains the second thyristor in an on state while maintaining the first thyristor and the switching element in an off state in a second period in which the absolute amplitude value is equal to or less than a second threshold value within the latter half of a second half-cycle of the input voltage at startup. The second half-cycle is the half-cycle following the first half-cycle.

Provided is a power supply apparatus that supplies power received from an external power supply to a load, the power supply apparatus comprising: a plurality of power supply circuitries, each of which has switching elements, that are allowed to supply power to the load separately; and a processor that controls a number of the power supply circuitries supplying power to the load according to a required power level of the load.