A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.

A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

An oscillator includes a first output node and a second output node. There is a tank circuit coupled between the first output node and the second output node. There is a first transistor having a first node, a second node coupled to a current source, and a control node coupled to the second output node. There is a second transistor having a first node, a second node coupled to the current source, and a control node coupled to the first output node. There is a first inductor coupled in series between the first node of the first transistor and the first output node. There is a second inductor coupled in series between the first node of the second transistor and the second output node.

A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

An isolated power transfer device includes a transformer formed in a multi-layer substrate of an integrated circuit package. A primary winding of the transformer is coupled to a first integrated circuit to form a DC/AC power converter and a secondary winding of the transformer is coupled to a second integrated circuit to form an AC/DC power converter. The first and second integrated circuits are electrically isolated from each other. The first integrated circuit includes a lightly doped drain MOSFET integrated with conventional CMOS devices and the second integrated circuit includes a Schottky diode integrated with conventional CMOS devices. The isolated power transfer device includes a capacitive channel for communication of information across an isolation barrier from the second integrated circuit to the first integrated circuit. Capacitors of the capacitive channel may be formed in the multi-layer substrate of the integrated circuit package.

A voltage controlled oscillator (VCO) and a method of operating the VCO are disclosed. The VCO includes an inductor device, a capacitor device coupled in parallel with the inductor device through first and second nodes, and a pair of cross-coupled transistors coupled in parallel with the inductor device and the capacitor device through the first and second nodes. At least one of the pair of cross-coupled transistor includes a plurality of sub transistors coupled in parallel. The sub transistors are individually switchable to adjust current drive capability of each of the sub transistors. Each of the sub transistors includes a first gate and a second gate.

A device and method for terahertz signal generation are disclosed. Oscillators are arranged in a two-dimensional array, each oscillator connected to a corresponding antenna. Each oscillator is unidirectional connected to its adjacent oscillators by a phase shifter. A method for generating a steerable terahertz signal utilizes an array of oscillators connected by corresponding phase shifters. A terahertz signal having a fundamental frequency is generated using the array. The phase shift of one or more of the phase shifters is varied in order to vary the fundamental frequency and/or steer the signal generated by the array.

A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.

The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

A resonator is supplied with voltage from a constant-voltage source, and the constant-voltage source outputs output voltage adjusted by a voltage adjustment signal to the resonator. The resonator outputs a clock signal having a frequency varied by varying capacitance in accordance with a received control signal and a frequency adjustment signal, and a frequency of the clock signal is varied by voltage output from the constant-voltage source.