A four-phase oscillator includes, a first oscillator configured to output a first differential signal, a second oscillator configured to output a second differential signal shifted in phase with respect to the first differential signal by 90 or 90 degrees, and a control circuit. The first oscillator includes a first tail current source and a second tail current source. The second oscillator includes a third tail current source and a fourth tail current source. The control circuit changes the frequency of the first and second differential signals by controlling at least one of a difference between a first current value supplied from the first tail current source and a third current value supplied from the third tail current source and a difference between a second current value supplied from the second tail current source and a fourth current value supplied from the fourth tail current source.

Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

A transconductance controlling circuit is provided. The transconductance controlling circuit includes a resonance circuit, a negative-resistance unit-circuit and a transconductance boosting circuit. The resonance circuit generates an oscillation signal. The negative-resistance unit-circuit is coupled to a resonance circuit and includes a first transistor and a second transistor. The transconductance boosting circuit is coupled to the negative-resistance unit-circuit and includes a third transistor and a fourth transistor. A first drain of the first transistor is coupled to a third drain of the third transistor, a first gate of the first transistor is coupled to a third gate of the third transistor, the first gate of the first transistor is coupled to a second drain of the second transistor, and a first base of the first transistor is coupled to a fourth base of the fourth transistor and to a fourth source of the fourth transistor.

Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.

A transconductance controlling circuit is provided. The transconductance controlling circuit includes a resonance circuit, a negative-resistance unit-circuit and a transconductance boosting circuit. The resonance circuit generates an oscillation signal. The negative-resistance unit-circuit is coupled to a resonance circuit and includes a first transistor and a second transistor. The transconductance boosting circuit is coupled to the negative-resistance unit-circuit and includes a third transistor and a fourth transistor. A first drain of the first transistor is coupled to a third drain of the third transistor, a first gate of the first transistor is coupled to a third gate of the third transistor, the first gate of the first transistor is coupled to a second drain of the second transistor, and a first base of the first transistor is coupled to a fourth base of the fourth transistor and to a fourth source of the fourth transistor.

A method for tuning a current source of a digitally controlled oscillator having an LC tank having a tunable capacitor bank includes: determining a specific threshold according to a resolution of a bit number of the tunable capacitor bank; configuring a current flowing through the current source at a first current level; tuning the current flowing through the current source from the first current level to a lower current level; comparing a variation of a digital value of the tunable capacitor bank with the specific threshold, the digital value corresponding to the lower current level; and determining that a current level required by the digitally controlled oscillator is decreased down to the lower current level and then configuring the current flowing through the current source at the lower current level if the variation of the digital value is smaller than the specific threshold.

A wireless communication apparatus includes an oscillator circuit configured to generate an oscillation signal corresponding to an oscillation frequency determined by an antenna, and a bias generator circuit configured to reconfigure an operation region mode of a transistor included in the oscillator circuit by adjusting a bias signal in response to an enable signal.

A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.

A frequency compensation circuit determines a target calibration count of a fixed capacitor coupled to a processing device. The frequency compensation circuit identifies a current calibration count of the fixed capacitor. The frequency compensation circuit determines that the current calibration count satisfies a threshold criterion associated with the target calibration count. In response to determining that the current calibration count satisfies the threshold criterion, the frequency compensation circuit adjusts a frequency of an internal oscillator of the processing device based on the current calibration count and the target calibration count.

An oscillator configured to generate an oscillation signal is provided. The oscillator includes a transistor pair and a cross-coupled transistor pair. The transistor pair is coupled to a first current source and has a first transconductance. The first transconductance is changed in response to a current value of the first current source. The cross-coupled transistor pair is coupled to a second current source and has a second transconductance. The second transconductance is changed in response to a current value of second current source. The transistor pair and the cross-coupled transistor pair are mutually coupled by a plurality of inductors. A frequency of the oscillation signal is determined according to the first transconductance and the second transconductance. Furthermore, a clock generator and a method for generating a clock signal thereof are also provided.