The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.

A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.

An apparatus is described that, according to an exemplary embodiment, has an RF oscillator for generating an RF oscillator signal at a first frequency and a frequency divider having a division ratio that is fixed during operation. The frequency divider is supplied with the RF oscillator signal and is configured to provide an oscillator signal at a second frequency. The apparatus further has a monitor circuit, to which the oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and to provide at least one digital value that is dependent on the second frequency of the oscillator signal. The at least one digital value is provided on a test contact.

Systems, methods, and circuitries are provided for generating timing signals with a resonator-based open-loop oscillator circuitry. In one example, a system that generates a timing signal based on a target signal includes a plurality of oscillator units configured to generate a respective plurality of oscillator signals. Each oscillator unit includes a resonator that operates in an open-loop mode to generate a resonator signal having a resonator frequency. The resonator signal is used by core circuitry to generate a respective oscillator signal having a respective oscillator frequency. The resonator frequencies of the resonators in the plurality of oscillator units are different from one another. The system also includes a selector circuitry configured to select one of the plurality of oscillator units based on the target signal and provide a selected oscillator signal generated by the selected oscillator unit as the timing signal.

A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

An apparatus is described that, according to an exemplary embodiment, has an RF oscillator for generating an RF oscillator signal at a first frequency and a frequency divider having a division ratio that is fixed during operation. The frequency divider is supplied with the RF oscillator signal and is configured to provide an oscillator signal at a second frequency. The apparatus further has a monitor circuit, to which the oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and to provide at least one digital value that is dependent on the second frequency of the oscillator signal. The at least one digital value is provided on a test contact.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Systems, methods, and circuitries are provided for generating timing signals with a resonator-based open-loop oscillator circuitry. In one example, a system that generates a timing signal based on a target signal includes a plurality of oscillator units configured to generate a respective plurality of oscillator signals. Each oscillator unit includes a resonator that operates in an open-loop mode to generate a resonator signal having a resonator frequency. The resonator signal is used by core circuitry to generate a respective oscillator signal having a respective oscillator frequency. The resonator frequencies of the resonators in the plurality of oscillator units are different from one another. The system also includes a selector circuitry configured to select one of the plurality of oscillator units based on the target signal and provide a selected oscillator signal generated by the selected oscillator unit as the timing signal.

An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.