Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.

A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.

Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.

A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

This disclosure relates to an apparatus, system, and method for generating uplink transmissions using a polar architecture including a phase locked loop with potential for two point injection. According to some embodiments, frequency resources allocated for a transmission may be determined. A cartesian baseband signal may be generated for the uplink transmission. The cartesian baseband signal may be converted to a polar baseband signal, including a baseband phase signal and an amplitude signal. Modulation parameters, potentially including whether to use one point injection or two point injection with a phase locked loop, may be determined. The baseband phase signal may be upconverted to an RF phase signal according to the determined modulation parameters. The RF phase signal may be amplified according to the amplitude signal to produce an RF signal. The RF signal may be transmitted.

The method for calibrating the frequency synthesiser using two-point FSK modulation consists, in a first phase, in supplying an excitation signal generated by a calibration unit to a sigma-delta modulator by deactivating a digital-to-analogue converter and transmitting the output signal from a loop filter of the synthesiser to the calibration unit, which digitally converts the incoming signal and offsets the phase shift between the excitation signal and the loop filter output signal in the calibration unit. In a second phase, the excitation signal is supplied to the sigma-delta modulator and to the activated digital-to-analogue converter, and the digital-to-analogue converter gain is calibrated by checking, in the calibration unit, the polarity of the loop filter output signal with respect to the excitation signal, and using a dichotomy algorithm.

Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.