A synthesizer comprises a first two-point modulation phase locked loop, TPM PLL, circuit that receives a first reference clock signal at a first reference frequency and a feedback signal at a feedback frequency and generates a first chirp signal by applying a two-point modulation PLL on the first reference clock signal, a second integer-n TPM PLL circuit that receives a second reference clock signal at a second reference frequency lower than the first reference frequency and generates a second chirp signal by applying a TPM PLL on the second reference clock signal, a mixer that downconverts the first chirp signal by the second chirp signal to obtain the feedback signal at the feedback frequency corresponding to the difference of the frequency of the first chirp signal and the second chirp signal, and a feedback path that feeds back the feedback signal to the first TPM PLL circuit.

In a PLL circuit, a multi-band control oscillator includes multiple bands gradually increasing or decreasing a frequency in accordance with a control signal and being separated from each other, is capable of selectively switching one band among the multiple bands, and generates a signal of a frequency corresponding to the control signal in the band that is switched as a reference signal. A band setting unit sets the band of the multi-band control oscillator. The band setting unit sets the band for a present or subsequent time after a control command generator finishes outputting the control command to gradually increase or decrease from a previous start frequency to a previous stop frequency and before the control command generator starts outputting the control command to gradually increase or decrease from a present start frequency.

A method of a control circuit of a communication device comprises: receiving a data signal to generate a phase data signal to a digital phase-locked loop (DPLL); using the DPLL to receive the phase data signal, to dynamically lock a particular clock, and to generate a phase modulation signal based on the phase data signal; and determining or adjusting an equivalent capacitance of an inter-stage circuit which is coupled between the DPLL and a power amplifier and configured for processing the phase modulation signal and generating a processed phase modulation signal to the power amplifier.

A synthesizer comprises a first two-point modulation phase locked loop, TPM PLL, circuit that receives a first reference clock signal at a first reference frequency and a feedback signal at a feedback frequency and generates a first chirp signal by applying a two-point modulation PLL on the first reference clock signal, a second integer-n TPM PLL circuit that receives a second reference clock signal at a second reference frequency lower than the first reference frequency and generates a second chirp signal by applying a TPM PLL on the second reference clock signal, a mixer that downconverts the first chirp signal by the second chirp signal to obtain the feedback signal at the feedback frequency corresponding to the difference of the frequency of the first chirp signal and the second chirp signal, and a feedback path that feeds back the feedback signal to the first TPM PLL circuit.

A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

An apparatus is described that, according to an exemplary embodiment, has an RF oscillator for generating an RF oscillator signal at a first frequency and a frequency divider having a division ratio that is fixed during operation. The frequency divider is supplied with the RF oscillator signal and is configured to provide an oscillator signal at a second frequency. The apparatus further has a monitor circuit, to which the oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and to provide at least one digital value that is dependent on the second frequency of the oscillator signal. The at least one digital value is provided on a test contact.