An example voltage controlled oscillator includes an inductor, a capacitor coupled to the inductor, and a signal source coupled to the inductor and the capacitor to sustain an oscillating signal. The voltage controlled oscillator includes a first varactor coupled to the inductor and the capacitor, wherein the first varactor is biased by a first bias voltage and is configured to change a frequency of the oscillating signal based on a first control voltage signal. The voltage controlled oscillator includes a second varactor coupled to the inductor, the capacitor, and the first varactor, wherein the second varactor is biased by a second bias voltage and is configured to compensate temperature variation of the frequency of the oscillating signal over a plurality of frequency bands based on second control voltage signal.

A wireless station includes at least one oscillator to output a reference signal, and an error calculator to calculate a frequency of the reference signal and calculate a frequency error by subtracting a target frequency of the reference signal from the calculated frequency of the reference signal. The wireless station further includes a modulation data generator to generate modulation data by adding a correction value, varying in negative correlation with the frequency error calculated by the error calculator, to data to be transmitted, and a modulator to conduct frequency modulation on the basis of the modulation data and the data to be transmitted.

A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

A frequency synthesizer circuit included in a sensor circuit of a computer system may include a voltage-controlled oscillator circuit that may generate an oscillator signal. A three-point injection technique may be used to modulate the frequency of the oscillator signal. The three-point injection includes a low-frequency component that drives a feedback divider, and two high-frequency components that drive the voltage-controlled oscillator circuit. The strengths of the three injection points are aligned using samples of a tune signal generated using results of a comparison of a referenced signal and a frequency divided version of the oscillator signal.

Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.

Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

Described is a high Q-factor inductor. The inductor is formed as a unit cell coil, which is copied twice for a dual-coil inductor and copied four times for a quad-coil inductor. For each copy of the unit cell coil, the coil is rotated a subsequent substantially 90 degrees or substantially 90 degrees. The rotation enables the terminals of the inductor to be routed equal-distant to a circuit that is placed in the line of symmetry between the two coils.