An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.

According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.

A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.

A sensor includes an analog front end having a circuit element responsive to a clock signal and a clock generating circuit configured to generate the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods. The blanking time periods correspond to time periods during which transitions of a common mode input voltage to the sensor are expected to occur.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

A gate driving circuit includes a pull-up control part for applying a first previous carry signal to a first node in response to the first previous carry signal, a first pull-up part outputting a clock signal as an N-th gate output signal in response to a signal applied to the first node, a second pull-up part outputting the clock signal as the N-th gate output signal in response to the signal applied to the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal applied to the first node, a first pull-down part pulling down the signal at the first node to a second off voltage, and a second pull-down part pulling down the N-th gate output signal to a first off voltage, wherein one of the first pull-up part and the second pull-up part is selectively activated.

A reception apparatus communicating with a transmission apparatus with a clock lane and a data lane. The reception apparatus comprises a clock lane control circuit configured to determine the operation mode of the clock lane based on a clock signal transmitted through the clock lane, and performing an operation based on the determined operation mode of the clock lane, and a data lane control circuit configured to determine the operation mode of the data lane based on a data signal transmitted from the transmission apparatus, and performing an operation based on the determined operation mode of the data lane, and the clock lane control circuit is configured to set the operation mode of the clock lane to a high-speed mode, when the operation mode of the data lane is switched from a low-power mode to the high-speed mode.

A clock converter to output a clock signal for testing a semiconductor device includes: a clock input terminal to receive an input clock having an input frequency; a first frequency conversion circuit to receive the input clock and output a first conversion clock having a first frequency by increasing the input frequency using a fixed multiplier; a second frequency conversion circuit to receive the input clock and output a second conversion clock having a second frequency, greater than the first frequency, by increasing the input frequency using a variable multiplier; and a selection circuit to output the first conversion clock or the second conversion clock according to a mode selection signal.

A synthesizer comprises a two-point modulation phase locked tow, TPM PLL, circuit configured to receive a frequency tuning signal and to generate a stepped chirp signal in an intermediate frequency range by applying a two-point modulation PLL on the frequency tuning signal, and a subsampling PLL circuit configured to receive the stepped chirp signal in a mm-wave frequency range and to generate a smoothened chirp signal in a mm-wave frequency range by applying a subsampling PLL on the stepped chirp signal.