A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.

A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.

A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

A frequency synthesizer circuit included in a sensor circuit of a computer system may include a voltage-controlled oscillator circuit that may generate an oscillator signal. A three-point injection technique may be used to modulate the frequency of the oscillator signal. The three-point injection includes a low-frequency component that drives a feedback divider, and two high-frequency components that drive the voltage-controlled oscillator circuit. The strengths of the three injection points are aligned using samples of a tune signal generated using results of a comparison of a referenced signal and a frequency divided version of the oscillator signal.

The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.

Various embodiments relate to a method for calibration of a center frequency of a BPF in an FSK transceiver, the method including the steps of filtering a carrier frequency signal by the BPF to produce a filtered signal, detecting, by a phase-frequency detector (PFD), a difference in phase between the carrier frequency signal and the filtered signal from the BPF, sweeping a calibration code of the BPF, detecting a transition in the sign of the phase difference and capturing a calibration code associated with the transition in the sign of the phase difference for calibration of the BPF.

A clock circuit includes a set of level shifters, and adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle, and is coupled to the adjustment circuit. The adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal and a second phase clock signal of the first set of phase clock signals, and adjust the first clock output signal and a second duty cycle of the first clock output signal responsive to a set of control signals. The calibration circuit is coupled to the adjustment circuit, and configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.