Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

Disclosed is technology related to a signal synthesis apparatus that corrects an offset between a closed loop and an open loop to output a frequency-modulated signal. The signal synthesis apparatus includes a VCO configured to modulate and output a frequency signal in response to an input voltage by including a modulation cap bank having a plurality of capacitors, an energy storage unit configured to output a voltage using stored energy, a VCO input selector configured to connect the VCO to input of the energy storage unit in the case of a closed loop mode and connect the VCO to output of the energy storage unit in the case of an open loop mode, and a digital controller configured to control an operation mode of the VCO input selector and transmit a modulation control signal for adjusting a connection state of the capacitors of the modulation cap bank to the VCO.

Disclosed is technology related to a signal synthesis apparatus that corrects an offset between a closed loop and an open loop to output a frequency-modulated signal. The signal synthesis apparatus includes a VCO configured to output a frequency signal in response to an input voltage, an energy storage unit configured to output a voltage using stored energy, a VCO input selector configured to connect the VCO to input of the energy storage unit in the case of a closed loop mode and connect the VCO to output of the energy storage unit in the case of an open loop mode, and a digital controller configured to control an operation mode of the VCO input selector and transmit an offset control signal for adjusting an offset of a voltage output from the energy storage unit to the energy storage unit.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a multiplexed selection signal, the first clock output signal having a second duty cycle; and adjust the second duty cycle responsive to at least a set of control signals or a phase difference between a first and second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to generate a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to adjust a second duty cycle of a first clock output signal responsive to a set of control signals or a phase difference between a first phase clock signal and a second phase clock signal of the first set of phase clock signals. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.