A complementary metal oxide silicon transceiver having an integrated power amplifier is provided. The complementary metal oxide silicon transceiver having the integrated power amplifier is capable of controlling an output power according to a communication environment to solve the following problem that with the increment of an output level of a power amplifier, performance is decreased when noises flow into other blocks of a transceiver with power and thus are inputted to the power amplifier.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.

Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.

A multimode power amplifier module, a chip and a communication terminal. In the module, a control circuit (104) sends a bias signal to a low-frequency power amplifier (102) or a high-frequency power amplifier (106) according to a baseband signal, so as to control the amplification of an accessed low-frequency radio frequency signal or a high-frequency radio frequency signal by the low-frequency power amplifier (102) or the high-frequency power amplifier (106); and a transceiving switch (108) selects a corresponding operation mode to conduct transmission or receiving according to an operation mode selection signal. A power amplification path is reused according to different modes, so that the power amplification path can be shared by different operation modes of a high and low frequency band with the adjustment of the control circuit (104), thus simplifying the complexity in designing the power amplifier module, and reducing the cost of relevant design implementation.

A method for controlling an envelope shape of an output signal outputted by a driver of a wireless transmitter includes supplying a first voltage level and a second voltage level, generating a filtered envelope reference signal by switching between the first voltage level and the second voltage level, in conjunction with low-pass filtering the transitions between the first voltage level and the second voltage level, generating a driver supply voltage following the filtered envelope reference signal, regulated in a manner adapted to supply the driver, and controlling the envelope shape of the output signal by supplying the driver with the driver supply voltage.

Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.

A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor

Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.

High efficiency transmit-receive switches in accordance with embodiments of the invention are disclosed. In one embodiment, a high efficiency transmit receive switch includes a power input coupled to a power supply, an amplifier output port and a transmit switch input port coupled to a circulator, a received signal circuit port coupled to a first PIN diode coupled to a second PIN diode via a first transmission line and spaced a fractional wavelength apart, the transmit switch input port is coupled to a third PIN diode coupled to a harmonic filter, a second transmission line coupled between the second PIN diode and to the third PIN diode, spaced a fractional wavelength apart, the transmit circuit signal port is coupled to an amplifier, the amplifier is coupled to the amplifier output port, the second transmission line is coupled to the bias current generator coupled to the output port.