A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.

Systems and methods are described for a power amplifier with a tracking power supply. The power amplifier may use envelope tracking. The power amplifier is protected when the output of the power amplifier is short circuited or overloaded.

Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.

An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.

Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.

A switching system is connected to the power amplifier of an RF system. The switching system can switch the DC supply voltage to the power amplifier while handling the high DC current and the nanosecond switching speed requirements that are mandatory for most RF systems. The embodiments can rapidly control DC voltages but not interfere with the optimized operation of the RF transistor. The embodiments provide a desired sharp turn-on leading edge for an RF pulse while eliminating the extremely long and undesirable ramp down that typically occurs beyond the desired RF pulse period.

An envelope tracking (ET) amplifier circuit is provided. In examples discussed herein, an amplifier circuit(s) is configured to amplify a radio frequency (RF) signal based on an ET modulated voltage. A tracker circuit is configured to generate the ET modulated voltage based on a number of target voltage amplitudes derived from a time-variant signal envelope of the RF signal. However, the tracker circuit can cause the ET modulated voltage to deviate from the target voltage amplitudes due to various impedance variations. In this regard, a voltage memory digital pre-distortion (mDPD) circuit digitally pre-distorts the target voltage amplitudes based on the time-variant signal envelope such that the ET modulated voltage can closely track the target voltage amplitudes. As such, it is possible to mitigate ET modulated voltage deviation, thus helping to improve overall linearity performance of the ET amplifier circuit.

The present disclosure relates to an amplification system that includes an amplifier, a resistor-capacitor (RC) network, and a charging path circuit. Herein, the RC network is coupled between an input port and an output port of the amplifier and includes a feedback resistor and a feedback capacitor. The feedback resistor is coupled between the input port of the amplifier and a joint point in between the feedback resistor and the feedback capacitor, and the feedback capacitor is coupled between the joint point and the output port of the amplifier. The charging path circuit is coupled between the joint point and ground, and configured to accelerate a charging speed of the feedback capacitor and reduce turn-on time of the amplifier.

A switching system is connected to the power amplifier of an RF system. The switching system can switch the DC supply voltage to the power amplifier while handling the high DC current and the nanosecond switching speed requirements that are mandatory for most RF systems. The embodiments can rapidly control DC voltages but not interfere with the optimized operation of the RF transistor. The embodiments provide a desired sharp turn-on leading edge for an RF pulse while eliminating the extremely long and undesirable ramp down that typically occurs beyond the desired RF pulse period.

A RF control circuit is provided and includes a controller, a divider, and a RF sensor. The controller selects a RF, which is a frequency of a reference LO signal. The divider receives a first RF signal detected in a substrate processing chamber and outputs a second RF signal. The first RF signal is generated by a RF generator and supplied to the substrate processing chamber. The RF sensor includes a lock-in amplifier, which includes: a RF path that receives the second RF signal; a LO path that receives the reference LO signal; a first mixer that generates an IF signal based on the second RF signal and the reference LO signal; and a filter that filters the IF signal. The controller generates a control signal based on the filtered IF signal and transmits the control signal to the RF generator to adjust the first RF signal.