A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

According to one aspect, embodiments of the invention provide an amplifier system comprising a first phase shifter configured to generate, based on an input signal, a first signal and a second signal, the second signal being out of phase with the first signal, a first amplifier configured to apply a first gain to the first signal to produce a gain adjusted first signal, a second amplifier configured to apply a second gain to the second signal to produce a gain adjusted second signal, a second phase shifter configured to combine the gain adjusted first and second signals to produce an output signal, and a controller configured to identify a high voltage swing across the first amplifier and, in response to identifying the high voltage swing, adjust the first gain to reduce output power of the first amplifier and adjust the second gain to increase output power of the second amplifier.

A system for adapting the voltage of a drain of a power stage includes at least two transmission paths T.sub.Xa, a transmission path comprising a resistive element (1.sub.n), a phase control module (2.sub.n), and a power stage (3.sub.n) at the output of which a radiating element (E.sub.n) is arranged, comprising at least: a device (5.sub.n) for determining the value of a reflected power P.sub.r, the value of an incident power P.sub.i in a power stage, and the ratio of the powers R, an analogue device (6.sub.n) configured so as to pulse width-modulate the difference signal, a switching cell (7.sub.n) receiving a low-power PWM signal and designed to generate a power signal PWM.sub.a that is transformed, by a low-pass filter (8.sub.n), into a bias signal for biasing the power stage in accordance with a predefined bias control law.

A balanced-to-Doherty (B2D) mode-reconfigurable power amplifier (PA) has the capability of maintaining high linearity and high efficiency against load mismatch. The reconfigurable PA includes a switch to alternatively connect to a pre-determined resistive load or a pre-determined pure reactive load (jX), i.e., short, open, or finite reactance between an output quadrature coupler and ground. The biasing of Doherty mode is adaptive dependent on the value of reactive loading (jX). The Doherty operation of this PA is based on an architecture configured from a balanced amplifier, e.g., a quasi-balanced amplifier.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

An amplifier circuit includes a circuit path of serially connected complementary type transistors. First and second feedback loops include a loop amplifier, the transistors of the circuit path and a corresponding resistor.

A cascode amplifier circuit comprising a power amplifier block having a first transistor and a second transistor. The amplifier circuit also comprises: a bias generator block coupled to the first transistor and being configured to provide a reference voltage to the power amplifier block; and a current control block coupled to the second transistor of the power amplifier block, the current control block being configured to adjust a gate bias to the second transistor of the power amplifier block to maintain a constant quiescent current.

A Digital Power-Amplifier (DPA) system includes a power amplifier (PA) circuit having control inputs and an output for generating output signals, and an adaptive control circuit that comprises an input interface, an output interface, a memory storing an adaptive control algorithm and a processor performing instructions based on the adaptive control algorithm in connection with the memory, wherein the input interface receives input-state signals and output signals of the DPA circuit, wherein the adaptive control algorithm determines, in response to the input-state signals and the output signals, control parameters of control signals transmitted to the control inputs from the output interface for controlling operations of the DPA circuit.

In certain aspects, a method is provided for measuring power using a resistive element coupled between a power amplifier and an antenna. The method includes squaring a voltage from a first terminal of the resistive element to obtain a first signal, squaring a voltage from a second terminal of the resistive element to obtain a second signal, and generating a measurement signal based on a difference between the first signal and the second signal. In some implementations, the resistive element is implemented with a power switch.

An apparatus is disclosed, comprising means for storing reference data indicative of characteristics for each of two or more amplifiers for amplifying signals in two or more respective bands, the reference data including voltage characteristics required by the particular amplifier to achieve a particular output power for a range of output power values for its respective frequency band. The apparatus may comprise means for receiving at least a first required output power for a first amplifier and a second required output power for a second amplifier, and determining, based on the reference data, the voltage characteristics required for the first amplifier to achieve the first required output power and the voltage characteristics required for the second amplifier to achieve the second required output power.