A system for split-frequency amplification, preferably including: one or more primary-band amplification stages, one or more secondary-band amplification stages, one or more band-splitting filters, and/or one or more signal couplers. An analog canceller including one or more split-frequency amplifiers. A mixer including one or more split-frequency amplifiers. A voltage-controlled oscillator including one or more split-frequency amplifiers. A method for split-frequency amplification, preferably including: receiving an input signal, separating the input signal into signal portions, and/or amplifying the signal portions, and optionally including combining the amplified signal portions and/or providing one or more output signals.

A system for split-frequency amplification, preferably including: one or more primary-band amplification stages, one or more secondary-band amplification stages, one or more band-splitting filters, and/or one or more signal couplers. An analog canceller including one or more split-frequency amplifiers. A mixer including one or more split-frequency amplifiers. A voltage-controlled oscillator including one or more split-frequency amplifiers. A method for split-frequency amplification, preferably including: receiving an input signal, separating the input signal into signal portions, and/or amplifying the signal portions, and optionally including combining the amplified signal portions and/or providing one or more output signals.

A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

An amplifier may comprise first and second matching networks; first and second transistors; and a transformer including first to third inductors. Also, a gate and a source of the first transistor are connected to the first matching network, one end of the first inductor is connected to a drain of the first transistor, the other end of the first inductor is connected to a source of the second transistor, one end of the second inductor is connected to a gate of the second transistor, the other end of the second inductor is grounded, one end of the third inductor is connected to a drain of the second transistor, and the other end of the third inductor is connected to the second matching network.

A power amplifier may comprise: an element for amplifying an electrical signal received through an input terminal, and outputting the amplified electrical signal through an output terminal; a first impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a fundamental component at the input terminal; a second impedance adjustment circuit connected to the input terminal of the element and adjusting impedance with respect to a frequency of a multiplied harmonic component at the input terminal; a third impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the fundamental component at the output terminal; a fourth impedance adjustment circuit connected to the output terminal of the element and adjusting impedance with respect to the frequency of the multiplied harmonic component at the output terminal; a first frequency separation circuit which prevents an impedance change by the first impedance adjustment circuit with respect to the frequency of the multiplied harmonic component at the input terminal, and prevents an impedance change by the second impedance adjustment circuit with respect to the frequency of the fundamental component at the input terminal; and a second frequency separation circuit which prevents an impedance change by the third impedance adjustment circuit with respect to the frequency of the multiplied harmonic component at the output terminal, and prevents an impedance change by the fourth impedance adjustment circuit with respect to the frequency of the fundamental component at the output terminal.

A reconfigurable low-noise amplifier (LNA) is disclosed. The reconfigurable LNA includes amplifier circuitry having a gate terminal coupled to an input terminal, a source terminal coupled to a fixed voltage node, and a drain terminal coupled to an output terminal. The reconfigurable LNA further includes a gamma inverting network (GIN) coupled between the input terminal and the fixed voltage node, wherein the GIN has a first switch configured to disable the GIN during operation at first frequencies within a lower frequency band relative to a higher frequency band and to enable the GIN during operation at second frequencies within the higher frequency band.

pHEMT-based switch circuits, devices including same, and methods of improving the linearity thereof. In one example, an antenna switch module includes a pHEMT switching circuit connected in series between an input signal terminal and a load terminal, the pHEMT switching circuit including at least one pHEMT configured to produce a first harmonic signal at the load terminal responsive to being driven by an input signal of a fundamental frequency received at the input signal terminal, the first harmonic signal having a first phase, and a gate resistance circuit connected to a gate of the at least one pHEMT and having a resistance value selected to produce a second harmonic signal at the load terminal, the second harmonic signal having a second phase opposite to the first phase.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.