A transmitter, a transmission system and a transmission method whereby AM-PM distortions can be compensated with high accuracy without affecting the functions of a predistortor, a ΔΣ modulator and so on. The transmitter includes: a baseband signal generation circuit that outputs the amplitude value and phase value of a baseband signal; a ΔΣ modulation circuit that performs a ΔΣ modulation of the outputted amplitude and phase values to output a pulse signal train; a power supply modulation circuit that supplies, to a pre-stage amplifier, a voltage determined in accordance with the outputted amplitude value; the pre-stage amplifier and a post-stage amplifier that amplify the outputted pulse signal train; and a filter circuit that generates an output signal from the pulse signal train as amplified and outputs the output signal. The power supply modulation circuit determines the voltage for canceling a phase error occurring in the post-stage amplifier.

An encoding modulation method and transmitter are described. The method includes: oversampling and noise-shaping received multi-bit data to obtain N bits of data; using the N bits of data as a lookup table address to obtain a PWM puke modulation signal; multiplexing synthetic orthogonal (IQ) complex data of the PWM pulse modulation signal to be real number signal data; and converting the multiplexed real number signal data to an analog signal for power amplification and output, N being an integer representing a smaller number of bits than the received multi-bit data.

A shaker test system with a class D power amplifier having an analog to digital converter to receive an analog input signal and convert the analog input signal to a digital signal, pulse width modulation logic coupled to the analog to digital converter to provide a delay time to a delay line to control a transition time of a pulse width modulated signal responsive to an output of the analog to digital converter, and a class D power output stage coupled to the delay line and responsive to the pulse width modulated signal to provide an output of the class D power amplifier stage. The class D amplifier allows use of a low cost microcontroller to obtain very small pulse width increments using a low cost microcontroller to provide a low cost shaker test system incorporating the class D power amplifier.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

A power amplifier includes an in-phase modulator configured to modulate an in-phase component of an input signal, a quadrature modulator configured to modulate a quadrature component of the input signal, and a processor configured to process the in-phase and quadrature components. The processor includes a clock configured to produce a clock signal, a pulse processor configured to remove non-essential information from the modulated in-phase and quadrature components, and a pulse converter configured to select an amplifier class and output a control signal based on the selected amplifier class. A switching network is also included and configured to actuate one or more switches based on the control signal to output an amplified signal.

An amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and an output node. The first capacitor is electrically connected between a first power supply node and a first node, the second capacitor is electrically connected between the first node and a second node, the third capacitor is electrically connected between a second power supply node and a third node, and the fourth capacitor is electrically connected between the third node and a fourth node. The first transistor has a gate node electrically connected to the second node, and the second transistor has a gate node electrically connected to the fourth node. The output node is selectively connected to the first transistor and the second transistor. The first node and the third node are configured to be selectively electrically connected to a voltage node and a common voltage node.

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.

Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.

An inverter circuit is provided. The inverter circuit includes a first node for coupling to a first electrical potential and a second node for coupling to a second electrical potential different from the first electrical potential. Further, the inverter circuit includes a third node configured to output an output signal of the inverter circuit. The inverter circuit includes a plurality of transistors of a first conductivity type coupled in series between the first node and the third node. Additionally, the inverter circuit includes a plurality of transistors of a second conductivity type coupled in series between the third node and the second node. The second conductivity type is different from the first conductivity type. The inverter circuit further includes at least one coupling path comprising a capacitive element. The at least one coupling path is coupled between a source terminal of one of the plurality of transistors of the first conductivity type and a source terminal of one of the plurality of transistors of the second conductivity type.

Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.