Pulse width modulators 131P and 131N respectively generate a first pulse Vp whose pulse width changes according to an input signal Vin based on the input signal Vin and a generated first carrier wave C1P, and a second pulse Vn whose pulse width changes according to the input signal Vin based on the input signal Vin and a generated second carrier wave C1N. Wherein due to the non-liner gradient in each of the generated first carrier wave C1P and the generated second carrier wave C1N and, duty ratio of each of the generated first pulse Vp and the generated second pulse Vn is less than 50% in a state where a value of the input signal is zero; and a difference between a pulse width of the first pulse Vp and a pulse width of the second pulse Vn linearly changes according to the input signal Vin.

A class-D amplifier includes: a gain control unit that amplifies an input audio signal in accordance with a compensation gain to generate an input signal Vin; and a pulse width modulator that generates a first pulse Vp whose pulse width changes according to the input signal Vin within a first input range A1 where a value of the generated input signal Vin is higher than a first boundary Vb1, and that generates a second pulse Vn whose pulse width changes according to the generated input signal Vin within a second input range A2. The gain control unit controls the compensation gain so that first inclination of an input/output characteristic of the class-D amplifier in a first section in which the pulse width modulator outputs both the first pulse Vp and the second pulse Vn and second inclination of the input/output characteristic in a second section other than the first section are similar to each other.

An amplifier circuit is capable of switching between a unipolar output voltage domain and a bipolar output voltage domain. The amplifier circuit comprises an operational amplifier with a feedback circuit that is configurable using switches. By controlling the switches, the amplifier's feedback circuit can switched between two different arrangements having a positive and a negative signal gain, respectively. The amplifier circuit is designed such that the noise gain is the same in both operating modes, allowing a single noise compensation approach to be used for both operating modes. Since configurability of the circuit is achieved using static switches, the amplifier circuit maintains high accuracy and experiences no appreciable impact on power consumption as a result of implementing the switching.

Systems and methods include a digital control module that receives and processes audio data for output through a loudspeaker. An analog block receives the audio data and the power control signal and amplifies the audio data for output. A first processing path includes a buffer to delay the audio data, a first component to combine the buffered audio data and anti-noise. A second processing path includes an absolute value block to receive the audio data and an envelope detector to receive the absolute value data and generate a maximum value for the envelope. An anti-noise path includes an absolute value block configured to determine an anti-noise absolute value which is combined with the absolute value anti-noise data. A power generator receives the output from the envelope detector and updates a power level to approximate a minimum powered needed to process the audio signal.

An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.

A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.

The signal processing device includes: an offset adjuster; an amplitude adjuster; and a delay adjuster, wherein the offset adjuster adjusts the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor, the amplitude adjuster adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster which is output when a first test signal is input to the signal processing circuit and (ii) the first test signal, and the delay adjuster adjusts the delay using a third parameter regarding the delay determined based on the difference signal that is an output of the subtractor when a second test signal is input to the signal processing circuit.

A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.

The present invention provides an offset calibration circuit used in a signal processing circuit, wherein the offset calibration circuit includes a supply voltage detection circuit and a calibration circuit. The supply voltage detection circuit is configured to detect a level of a supply voltage to generate a detection result, wherein the supply voltage is provided to an output stage in the signal processing circuit. The calibration circuit is configured to calculate a digital compensation value according to the detection result, wherein the digital compensation value is used for a digital processing circuit in the signal processing circuit to perform a DC offset calibration.