An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.

A CMOS amplifier including electrostatic discharge (ESD) protection circuits is disclosed. In one embodiment, the CMOS amplifier may include a PMOS transistor, a NMOS transistor, primary protection diodes, and one or more auxiliary protection diodes to limit a voltage difference between terminals of the CMOS amplifier. In some embodiments, the auxiliary protection diodes may limit the voltage difference between an input terminal of the CMOS amplifier and a supply voltage, the input terminal of the CMOS amplifier and ground, and the input terminal and the output terminal of the CMOS amplifier.

A capacitor weighted segmentation buffer includes a push-pull buffer circuit and a plurality of capacitors. The capacitors include a first capacitor having a first terminal coupled to a control terminal of the first transistor and a second terminal arranged to receive a first input signal; a second capacitor having a first terminal coupled to a control terminal of the second transistor and a second terminal arranged to receive the first input signal; a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal arranged to receive a second input signal; and a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the second input signal.