Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.

Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.

The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.

An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.

An amplifier comprising an active device having an output terminal for driving a load impedance in response to a signal applied to an input terminal and a current source connected to the active device to provide a bias to the active device wherein when the active device is operated an output power of the active device increases with increasing load impedance.

An optical receiver includes: a light reception element to convert an input optical signal into a first current signal and output the first current signal; an inverter-based TIA to convert the first current signal into a voltage signal and output the voltage signal using first and second field effect transistors; a current monitor unit to monitor a current magnitude of the first current signal and output a second current signal having a current magnitude based on the current magnitude of the first current signal; and a back-gate adjustment unit to determine a state of an input-output characteristic of the inverter-based TIA on the basis of the second current signal and the voltage signal, and control, on the basis of the determination result, a back-gate terminal voltage of at least one of the first and second field effect transistors.

The present invention discloses a power amplifier capable of adaptively operating in one of an energy efficient mode and a high output power mode. An embodiment of the power amplifier includes a first transistor, a second transistor, a first bias element, a second bias element, a third bias element and a plurality of switches. In the energy efficient mode, by the control over the on/off states of the switches, an inverter type power amplifier is realized with the first transistor, the second transistor, the second bias element and the third bias element. In the high output power mode, by the control over the on/off states of the switches, a common source amplifier or a common emitter amplifier is realized with the second transistor and the first bias element.

An inverting amplifier includes an input terminal, an output terminal, a PMOS transistor, another PMOS transistor, an NMOS transistor, another NMOS transistor, and a clamp circuit. The PMOS transistors are connected in series between a supply voltage and an output terminal. The NMOS transistors are connected in series between a ground voltage and the output terminal. The clamp circuit is connected to the gate of the other PMOS transistor and the gate of the other NMOS transistor. The clamp circuit includes a switch, a capacitor, another switch, and another capacitor. At least one of the gate of the PMOS transistor and the gate of the NMOS transistor is connected to the input terminal.

The present invention discloses a power amplifier capable of adaptively operating in one of an energy efficient mode and a high output power mode. An embodiment of the power amplifier includes a first transistor, a second transistor, a first bias element, a second bias element, a third bias element and a plurality of switches. In the energy efficient mode, by the control over the on/off states of the switches, an inverter type power amplifier is realized with the first transistor, the second transistor, the second bias element and the third bias element. In the high output power mode, by the control over the on/off states of the switches, a common source amplifier or a common emitter amplifier is realized with the second transistor and the first bias element.

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.