An apparatus includes a plurality of transmitter channels and a plurality of feedback networks. Each of the plurality of transmitter channels may be coupled to a respective antenna element in a respective group of antenna elements of a phased array antenna. Each of the transmitter channels generally comprises a power amplifier circuit configured to drive the respective antenna element in the respective group of antenna elements to produce and steer a radio-frequency beam. Each of the plurality of feedback networks may be coupled between an output and an input of a respective power amplifier circuit of a respective transmitter channel. Each of the feedback networks generally comprises a resistor and a capacitor connected in series. The respective power amplifier circuit with the feedback network generally maintains a power matching condition with load variation associated with performing beam steering of the radio-frequency beam using the antenna elements of the phased array antenna.

A differential power amplifier (DPA) includes an p-side and a n-side half circuit. The p-side and n-side half circuits include an p-side and n-side base, which receive respective in-phase and out-of-phase signals of a differential signal. The DPA includes an p-side biasing circuit and a n-side biasing circuit. The p-side and n-side biasing circuit are configured to provide a controllable p-side and n-side biasing signal to the p-side and n-side base, respectively. The DPA includes a power source which provides positive DC voltage to the controller of the p-side and n-side half circuits. The DPA includes supply and grounding circuit structure which provides common mode DC paths and balances the n-side and p-side half circuits to provide a radio frequency (RF) virtual ground to an emitter of the n-side half circuit and p-side half circuit.

A transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The transistor amplifier exhibits improved input impedance and improved linearity.

An amplifier circuit includes a potential relation between a common emitter amplifier circuit (amplifier circuit body) including an NPN transistor (bipolar transistor) and a clamp circuit which maintains a potential relation between a base-collector of the NPN transistor of the common emitter amplifier circuit. The clamp circuit includes a level shift circuit and a clamp diode for suppressing a decrease in the collector potential of the NPN transistor of the common emitter amplifier circuit.

A power amplifier circuit for broadband data communication over a path in a communication network can reduce or avoid gain compression, provide low distortion amplification performance, and can accommodate a wider input signal amplitude range. A dynamic variable bias current circuit can be coupled to a differential pair of transistors to provide a dynamic variable bias current thereto as a function of input signal amplitude. Bias current is increased when input signal amplitude exceeds a threshold voltage established by an offset or level-shifting circuit. The frequency response of the bias current circuit can track the full frequency content of the input signal, rather than its envelope. Gain degeneration can be modulated in concert with the bias current modulation to stabilize amplifier gain.

A method for rapidly gathering a sub-threshold swing from a thin film transistor is provided. The method includes: electrically connecting an operational amplifier and an anti-exponential component to a source terminal of the thin film transistor; performing a measuring process to the thin film transistor in which the measuring process is inputting multiple values of a gate voltage to a gate terminal, such that multiple values of an output voltage are correspondingly generated from the output terminal of the operational amplifier; and performing a fitting process to the output voltage corresponding to the thin film transistor in which the fitting process is fitting at least two of said multiple values of the output voltage to get the sub-threshold swing.

An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2.Math.fc.Math.C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.

An analog computing method includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.