Techniques are described for power detection of an amplified signal. For example, power detection described herein can receive an amplified signal from a power amplifier, and can generate an output signal that can be fed back to help regulate an output level of the power amplifier. Embodiments receive the amplified signal can be received by a transistor. A first measurement can be obtained at the transistor's emitter corresponding to an average bias level of the amplified signal, and a second measurement can be obtained at the transistor's base. The output signal can be generated as a function of a difference between the two measurements. Some embodiments further compensate for a measured effective diode voltage corresponding to a base-emitter voltage. Such an approach can generate the power detector output signal to be independent of the of the transistor, and therefore less affected by variations in process corners and temperature.

An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.

An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.

An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

An apparatus includes a plurality of transmitter channels and a plurality of feedback networks. Each of the plurality of transmitter channels may be coupled to a respective antenna element in a respective group of antenna elements of a phased array antenna. Each of the transmitter channels generally comprises a power amplifier circuit configured to drive the respective antenna element in the respective group of antenna elements to produce and steer a radio-frequency beam. Each of the plurality of feedback networks may be coupled between an output and an input of a respective power amplifier circuit of a respective transmitter channel. Each of the feedback networks generally comprises a resistor and a capacitor connected in series. The respective power amplifier circuit with the feedback network generally maintains a power matching condition with load variation associated with performing beam steering of the radio-frequency beam using the antenna elements of the phased array antenna.

A supply voltage control circuit for a display panel, a display panel and a display device, wherein the supply voltage control circuit includes: a clock, a first conductive device, a second conductive device and an operational amplifying device; the supply voltage control circuit is configured to amplify supply voltage.

An apparatus includes a phased array antenna panel and one or more beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of antenna elements are generally arranged in one or more groups. The one or more beam former circuits may be mounted on the phased array antenna panel. Each beam former circuit is generally coupled to a respective group of the antenna elements. Each beam former circuit generally comprises a plurality of transceiver channels comprising a transmit channel and a receive channel. The phased array antenna panel is generally configured to distribute a control signal to each of the beam former circuits. Each of the transceiver channels is generally configured to switch between a transmit mode and a receive mode in response to the control signal.

A unity gain buffer provides an ON state in which the input signal is coupled to the output terminal and an OFF state in which the input signal is isolated from the output terminal. Multiple unity gain buffers may share the same load to form a voltage-mode maximum follower or a multiplexer.

A supply voltage control circuit for a display panel, a display panel and a display device, wherein the supply voltage control circuit includes: a clock, a first conductive device, a second conductive device and an operational amplifying device; the supply voltage control circuit is configured to amplify supply voltage.

An apparatus includes a plurality of transceiver circuits and a plurality of feedback networks. Each of the plurality of transceiver circuits may be coupled to a respective antenna element in a respective group of antenna elements of a phased array antenna. Each of the transceiver circuits generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive the respective antenna element in the respective group of antenna elements. Each of the plurality of feedback networks may be coupled between an output and an input of a respective power amplifier circuit of a respective transceiver circuit. Each of the feedback networks generally comprises a resistor and a capacitor connected in series. The respective power amplifier circuit with the feedback network generally maintains a power matching condition with load variation associated with the antenna elements of the phased array antenna.