Methods and apparatus for a pixel system for providing power supply noise rejection. A photodetector has a first terminal coupled to a voltage supply and a second terminal and a differential transimpedance amplifier has a first input coupled to the second terminal of the photodetector. The differential transimpedance amplifier is configured to convert a singled ended output on the second terminal of the photodetector to a differential signal. A bias circuit is coupled to the differential transimpedance amplifier to bias the differential transimpedance amplifier and the photodetector.

Methods and apparatus for a pixel system for capturing active imaging data. The system includes a photodetector having a first terminal coupled to a voltage supply and a second terminal and a differential transimpedance amplifier having a first input coupled to the second terminal of the photodetector. A voltage discriminator has an input coupled to an output of the differential transimpedance amplifier and an output.

Methods and apparatus for a pixel system for correction of non-uniform photo-detector and pixel gains. The system includes a photodetector having a first terminal coupled to a voltage supply and a second terminal, a differential transimpedance amplifier having a first input coupled to the second terminal of the photodetector, and a bias circuit coupled to the differential transimpedance amplifier to set common mode feedback for the differential transimpedance amplifier and to set bias of the photodetector for correcting non-uniform photodetector gain. A digital-to-analog converter is coupled to the bias circuit to output multiple discrete voltage levels.

The present document relates to differential amplifiers. A differential amplifier may comprise a current source, a first transistor, a second transistor, and a compensation circuit. A reference voltage may be applied to a first terminal of the first transistor, and a second terminal of the first transistor may be coupled to an output of the current source. A feedback voltage may be applied to a first terminal of the second transistor, and a second terminal of the second transistor may be coupled to the output of the current source. The compensation circuit may comprise a capacitive element coupled to the first terminal of the first transistor, and the compensation circuit may be configured to reduce a change of the reference voltage at the first terminal of the first transistor.

A high CMRR current monitoring circuit includes a first stage that receives a current sense signal, a voltage across a current sense resistor in series with an output of a class-D amplifier. First stage is powered by at least one floating supply and/or reference that tracks the amplifier output. First stage applies gain to the current sense signal to generate an intermediate signal. A second stage receives the intermediate signal and is powered by a ground-referenced supply and provides an amplified representation of the current sense signal. The floating supply is supplied by a capacitive-coupled power source driven by the ground-referenced supply. The second stage output may be a voltage relative to ground or a digital signal. The intermediate signal may be a current, digital signal, or amplified version of the current sense signal voltage. The first stage may be a transconductance amplifier and the second stage a transimpedance amplifier.

A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

A differential operational transconductance amplifier, or DOTA, intended to be used in zero-drift precision operational amplifiers as chopper amplifier stage is disclosed. The DOTA is configured to function with a low-voltage power supply and to have good performance based on circuitry configured to provide a constant gain over a range of common-mode voltages, or VCM. The DOTA further includes bias circuitry configured to respond to the common mode voltage in order to prevent large currents, which can result from the constant gain circuitry, from negatively affecting performance. The DOTA further includes current sources that are configured to prevent temperature variations from negatively affecting performance. The DOTA further includes VCM-driven bias voltages used to optimize the operating point of the differential output stage. The DOTA uses input and input replica transistors having medium threshold voltage, which results in capability to operate at low supply voltages.

A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET, An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents. In a next reset phase, the second capacitor holds a multiplied value of charge.

A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.

A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents. In a next reset phase, the second capacitor holds a multiplied value of charge.