Systems and methods for amplifying an input signal include amplifier circuitry, an itail connection coupled between a positive voltage circuitry and the negative voltage circuitry and operable to generate an itail voltage corresponding to a greater of the positive voltage input signal (Vp) and the negative voltage input signal (Vn), a first resistor rgp disposed to receive the itail voltage and a first voltage corresponding to Vp, and a second resistor rgn disposed to receive the itail voltage and a second voltage corresponding to Vn. A first current output node is coupled to the output of rgp and operable to output a positive output current (Ioutp) corresponding to the current flowing through rgp, and a second current output is coupled to the output of rgn and operable to output a negative output current (Ioutn) corresponding to the current flowing through rgn.

The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include a phase distortion compensation circuit that can compensate for input impedance variations that could otherwise lead to reduced efficiency and power performance. In one specific embodiment, the phase distortion compensation circuit is used to compensate for input impedance variations in the peaking amplifiers of a Doherty amplifier. In such embodiments, the phase distortion compensation circuit can absorb the non-linear input impedances of the peaking amplifiers in a way that may facilitate improved phase maintenance between the carrier and peaking stages of the Doherty amplifier.

A power amplifying apparatus includes a first bias circuit configured to generate a first bias current, a first amplification circuit, configured to receive the first bias current, amplify a signal input to the first amplification circuit through a first node, and output a first amplified signal to a second node, a second bias circuit, configured to generate a second bias current which has a magnitude different from a magnitude of the first bias current, and a second amplification circuit, connected in parallel with the first amplification, configured to receive the second bias current, amplify the signal input through the first node, and output a second amplified signal to the second node. The second amplification circuit is configured to output the second amplified signal with a third-harmonic component that has a phase offsetting a third-order intermodulation distortion (IM3) component included in the first amplified signal, based on the second bias current.

A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

A power amplification system with shared common base biasing is disclosed. A method for power amplification at a controller of a power amplification system comprising a plurality of cascode amplifier sections can include receiving a band select signal indicative of one or more frequency bands of a radio-frequency input signal to be amplified and transmitted. The method may further include biasing a common base stage of each of the plurality of cascode amplifier sections, and biasing a common emitter stage of a subset of the plurality of cascode amplifier sections.

Circuits, devices and methods related to amplification with active gain bypass. In some embodiments, an amplifier can include a first amplification path implemented to amplify a signal, and having a cascode arrangement of a first input transistor and a cascode transistor to provide a first gain for the signal when in a first mode. The amplifier can further include a second amplification path implemented to provide a second gain for the signal while bypassing at least a portion of the first amplification path when in a second mode. The second amplification path can include a cascode arrangement of a second input transistor and the cascode transistor shared with the first amplification path. The amplifier can further include a switch configured to allow routing of the signal through the first amplification path in the first mode or the second amplification path in the second mode.

A digital power amplifier comprising two or more individually activatable amplifiers. The outputs of the amplifiers are connected causing an activated amplifier of the two or more amplifiers to load modulate another activated amplifier of the two or more amplifiers.

A power amplifier module includes first and second amplifiers, a first bias circuit, and an adjusting circuit. The first amplifier amplifies a first signal. The second amplifier amplifies a second signal based on an output signal from the first amplifier. The first bias circuit supplies a bias current to the first amplifier via a current path on the basis of a bias drive signal. The adjusting circuit includes an adjusting transistor having first, second, and third terminals. A first voltage based on a power supply voltage is supplied to the first terminal. A second voltage based on the bias drive signal is supplied to the second terminal. The third terminal is connected to the current path. The adjusting circuit adjusts the bias current on the basis of the power supply voltage supplied to the first amplifier.