Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

Circuits, devices and methods related to multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module.

A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

An envelope tracking power amplifier is disclosed herein. The envelope tracking power amplifier includes a multi-mode bias modulator and a power amplifier. The multi-mode bias modulator generates an envelope-modulated bias voltage from the envelope signal of an radio frequency (RF) signal whose power is to be amplified by using a linear amplifier and a switching amplifier each having varying current driving capability in response to an operation mode control signal that determines any one of low-level mode and high-level mode. The power amplifier is biased in response to the envelope-modulated bias voltage, amplifies the RF signal, and outputs the amplified RF signal to an antenna.

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

Disclosed is an amplifier having a carrier amplifier configured as a common-emitter carrier power stage and a peaking amplifier configured as a common-emitter peaking power stage. Further included is power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

Disclosed is an amplifier having a carrier amplifier configured as a common-emitter carrier power stage and a peaking amplifier configured as a common-emitter peaking power stage. Further included is power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

A clamp circuit comprises a first diode stack comprising one or more diodes and an array comprising a second diode stack comprising one or more diodes and a comparator configured to compare a first voltage at the first diode stack to a second voltage at the second diode stack.