A digital power amplifier comprising at least two individually activatable amplifiers connected to an output network comprising a first hybrid coupler. An output of a first amplifier is connected to a first input of the first hybrid coupler and an output of a second amplifier is connected to a second input of the first hybrid coupler such that activating an amplifier of the at least two amplifiers causes the amplifier to load modulate another activated amplifier of at least two amplifiers.

An embodiment of a dual-path amplifier includes a power splitter connected to first and second power amplifiers respectively connected to first and second transmission lines connected to a power combiner having a phase-offset deficit at the second harmonic frequency 2f0, where the first and second transmission lines are designed to provide a complementary phase offset at 2f0 substantially equal to the phase-offset deficit such that the two amplified signals will be combined at the power converter with a total phase offset at 2f0 of about 180 degrees in order to reduce harmonic distortion in the amplified output signal, without substantially diminishing the output power at the fundamental frequency f0. In certain PCB-based implementations, the transmission lines include metal traces and lumped elements providing different impedance transformations that achieve the complementary phase offset, where the metal traces may have significantly different physical and electrical characteristics.

An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

Methods and architectures for closed loop digital pre-distortion (DPD) in a multi-stream phased array communication system include sampling outputs, from transmit antennas or dedicated analog detectors, of a plurality of RF power amplifiers operating in transmission of multi-stream transmission, correcting or normalizing the detected outputs, summing the outputs into a combined DPD feedback signal and selecting pre-distortion vectors to be used in altering the output of the PAs.

An amplifier for a transceiver comprising

plurality of power amplifiers arranged on a base, each power amplifier comprising a power amplifier input port and a power amplifier output port;

a planar power splitter arranged on the base, the power splitter comprising a power splitter input port and a plurality of power splitter output ports;

each power amplifier input port being connected to a power splitter output port by a planar transmission line;

each power amplifier output port being connected to a waveguide transition;

a plurality of waveguides each defined by a waveguide wall, each waveguide being arranged within the base, each waveguide transition being connected to waveguide; and,

a waveguide power combiner arranged within the base, each waveguide being connected to the waveguide power combiner.

Methods and apparatus for implementing a power efficient amplifier device through the use of a main (primary) and auxiliary (secondary) power amplifier are described. The primary and secondary amplifiers operate as current sources providing current to the load. Capacitance coupling is used to couple the primary and secondary amplifier outputs. In some embodiments the combination of primary and secondary amplifiers achieve high average efficiency over the operating range of the device in which the primary and secondary amplifiers are used in combination as an amplifier device. The amplifier device is well suited for implementation using CMOS technology, e.g., N-MOSFETs, and can be implemented in an integrated circuit space efficient manner that is well suited for supporting RF transmissions in the GHz frequency range, e.g., 30 GHz frequency range. The primary amplifier in some embodiments is a CLASS-AB or B amplifier and the secondary amplifier is a CLASS-C amplifier.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port and a second differential transistor pair. The CTLE circuit further includes a first degenerative impedance circuit coupled between the first differential transistor pair and ground. The first degenerative impedance includes switchable components to vary impedance of the first degenerative impedance circuit. The CTLE circuit also includes a second degenerative impedance circuit coupled between the second differential transistor pair and ground. The second degenerative impedance includes switchable components to vary impedance of the second degenerative impedance circuit, wherein the resistive part of the impedance of the first degenerative impedance circuit is equal to the impedance of the second degenerative impedance circuit.

A Doherty amplifier includes a carrier amplifier, a peaking amplifier, and a phase compensation circuit. The carrier amplifier 11 includes a main amplifying element and a parasitic element, and the peaking amplifier includes an auxiliary amplifying element and a parasitic element. The phase compensation circuit has a negative electrical length that allows a total electrical length of a signal transmission path starting from an output source of the main amplifying element to a power combiner to become 180N90 where N is a positive integer. In addition, a signal transmission path starting from an output source of the auxiliary amplifying element to the power combiner has an electrical length of 180M180 where M is a positive integer.

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.