Circuits and methods related to power amplifiers. Power density matching circuits can be provided to match power densities in reference devices and amplifying devices. In some implementations, a power density matching circuit includes a temperature independent current translator with a first transistor and a third transistor coupled emitter to collector between a power supply node and ground and a second transistor and a fourth transistor coupled emitter to collector between the power supply node and ground. The transistors of the current translator can be sized relative to one another to set a current density in the amplifying transistor relative to a current density in the reference transistor. The current translation can provide power density matching between the amplifying transistor and the reference transistor.

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

A power amplifier circuit includes a transistor, a bias current source, and an adjustment circuit. The transistor amplifies an RF signal when supplied with a variable power supply voltage. The bias current source supplies a bias current to the base of the transistor through a first current path. The adjustment circuit increases a current flowing from the bias current source to an input terminal of a matching circuit through a second current path as the variable power supply voltage decreases, and decreases the bias current flowing from the bias current source to the base of the transistor through the first current path as the current flowing from the bias current source to the input terminal through the second current path increases.

A radio-frequency device comprises a first radio-frequency signal node, a second radio-frequency signal node, a first power cell path coupled between the first radio-frequency signal node and a ground reference node, the first power cell path including a first transistor having an input terminal coupled to the second radio-frequency signal node, and a second power cell path coupled in parallel with the first power cell path between the first radio-frequency signal node and the ground reference node, the second power cell path including a second transistor having an input terminal coupled to the second radio-frequency signal node and an output terminal that is electrically isolated from an output terminal of the first transistor.

In some embodiments, a filtering technique can include a pre-amplifier filter configured to filter a signal, and an amplifier assembly configured to amplify the filtered signal. The filtering technique can further include a filter circuit configured to provide selective filtering of the amplified signal based at least in part on a rejection level of the pre-amplifier filter and a gain of the amplifier assembly.

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

A cascode power cell for a power amplifier circuit includes a radio frequency signal input node, a radio frequency signal output node, and a plurality of sub-cells each including a first transistor having a collector coupled to the radio frequency signal output node, each of the plurality of sub-cells further including a second transistor having a collector coupled to an emitter of the first transistor at a connection node, and a base coupled to the radio frequency signal input node, the connection nodes for each of the plurality of sub-cells being electrically isolated from one another.

Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a differential amplifier connectable to receive the first electrical supply level, the differential amplifier having a first input connectable to a first node of the reference device and a second input connectable to receive a reference electrical level, the differential amplifier arranged to maintain a first electrical level on the first node of the reference device as a function of the reference electrical level.

Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

A variable load power amplifier that improves the performance of a power amplifier that provides both envelope tracking (ET) and average power tracking (APT). The variable load power amplifier can include a plurality of amplifiers that are each selectively connectable into one of a plurality of parallel combinations, each of the plurality of parallel combinations characterized by a corresponding load line. The variable load power amplifier can also include a plurality of control elements arranged to selectively connect one or more of the plurality of amplifiers into one of the plurality of parallel combinations, each of the plurality of control elements having a respective input terminal provided to receive a respective control signal, each of the plurality of control elements responsive to the respective control signal.