A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

Various buck-boost amplifier architectures are disclosed. In some architectures, a plurality of amplifiers use one or more inductors from a shared bank of inductors as needed to deliver variable amounts of power to respective loads. In some architectures, each amplifier includes multiple inductors and switches that are controlled to vary the number of inductors used in an amplifier based on a power requirement of the amplifier to drive its load. In some architectures, the switches include well switching devices. In some architectures, each amplifier drives multiple loads and is operated in a single inductor multiple output (SIMO) mode. In all architectures, the loads include speakers, piezo elements, and motors.

Certain aspects of the present disclosure provide a switch architecture for switching between a low power amplifier and a high power amplifier. One example amplification system includes a high power amplifier and a low power amplifier. The amplification system further includes a first switch coupled between the high power amplifier and an output. The amplification system further includes a second switch coupled between the output and a reference potential. The second switch is further coupled between the low power amplifier and the output and configured to selectively couple the low power amplifier to the output. The amplification system further includes a third switch coupled between the low power amplifier and the second switch.

A variable load power amplifier that improves the performance of a power amplifier that provides both envelope tracking (ET) and average power tracking (APT). The variable load power amplifier can include a plurality of amplifiers that are each selectively connectable into one of a plurality of parallel combinations, each of the plurality of parallel combinations characterized by a corresponding load line. The variable load power amplifier can also include a plurality of control elements arranged to selectively connect one or more of the plurality of amplifiers into one of the plurality of parallel combinations, each of the plurality of control elements having a respective input terminal provided to receive a respective control signal, each of the plurality of control elements responsive to the respective control signal.

A power amplification system comprises a pre-processor including a wavefront multiplexer, a set of power amplifiers, and a post-processor including a wavefront demultiplexer. The wavefront multiplexer receives concurrently N input signals, N being an integer greater than 2, performs a wavefront multiplexing transform on the N input signals by attaching N wavefronts to the N input signals respectively, and generates N first output signals. The N wavefronts are unique and mutually orthogonal. The wavefront multiplexing transform has an inverse. The N power amplifiers amplify the N first output signals and generate N amplified signals. The wavefront demultiplexer performs the inverse of the wavefront multiplexing transform on the N amplified signals and generates N second output signals, the N second output signals corresponding respectively to the N input signals. Each of the N second output signals is an amplified version of a corresponding one of the N input signals.

A broadband linear processing system includes a pre-processing module and a set of M linear processors coupled to the pre-processing module, M being an integer greater than 1. The pre-processing module includes a wavefront multiplexer having M input ports and M output ports. The wavefront multiplexer receives M input signals at the M input ports, performs a wavefront multiplexing transform on the M input signals and outputs M narrowband signal streams at the M output ports. The wavefront multiplexing transform has an inverse. Each of the M linear processors receives and processes a corresponding one of the M narrowband signal streams, and outputs a corresponding one of M processed narrowband signal streams.

A power amplifier circuit, including: an input node configured to receive a radio frequency (RF) signal; an output node configured to output an amplified RF signal; a main path switchably coupled between the input node and the output node, and including a first plurality of amplification stages to generate a first amplified RF signal; a bypass path switchably coupled between the input node and the output node, and including at least one second amplification stage to generate a second amplified RF signal; and a coupling switch configured to reuse at least a portion of the bypass path to drive the main path to generate a third amplified RF signal.

A multi-band power amplifier module includes at least one transmission input terminal, at least one power amplifier circuit that receives a first transmission signal and a second transmission signal through the at least one transmission input terminal, a first filter circuit that allows the first transmission signal to pass therethrough, a second filter circuit that allows the second transmission signal to pass therethrough, at least one transmission output terminal through which the first and second transmission signals output from the first and second filter circuits are output, a transmission output switch that outputs each of the first and second transmission signals output from the at least one power amplifier circuit to the first filter circuit or the second filter circuit, and a first tuning circuit that adjusts impedance matching between the at least one power amplifier circuit and the at least one transmission output terminal.

A variable load power amplifier that improves the performance of a power amplifier that provides both envelope tracking (ET) and average power tracking (APT). The variable load power amplifier can include a plurality of amplifiers that are each selectively connectable into one of a plurality of parallel combinations, each of the plurality of parallel combinations characterized by a corresponding load line. The variable load power amplifier can also include a plurality of control elements arranged to selectively connect one or more of the plurality of amplifiers into one of the plurality of parallel combinations, each of the plurality of control elements having a respective input terminal provided to receive a respective control signal, each of the plurality of control elements responsive to the respective control signal.

A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2 Vbe) of the amplifying transistor.