Methods, systems, and devices for wireless communications are described. A first user equipment (UE) may receive, from a second UE, a control message that indicates a duration of time the second UE has reserved at least a first subchannel of a first subband of a set of shared spectrum subbands. The duration of time may include a quantity of time periods. The first UE may transmit, during a time period of the quantity of time periods and in a second subchannel of the first subband, a power reservation signal that indicates a transmission power associated with the first UE beginning transmission to a third UE in a second subband of the set of shared spectrum subbands and partway through the time period. The first UE may transmit signaling to the third UE in the second subband partway through the time period and after transmitting the power reservation signal.

Certain aspects of the present disclosure provide techniques for configuring sidelink slots with multiple automatic gain control symbols. One aspect provides a method for wireless communication by a user equipment, including enabling a slot configuration comprising at least two symbols configured for use by a receiver for automatic gain control in preconfigured symbol locations within a slot, and transmitting the at least two symbols while transmitting symbols within the slot.

Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.

A high-frequency (HF) driver circuit for an acousto-optical component includes an HF power amplifier connected to a voltage regulator for supply with a supply voltage and a bias voltage generator connected to an input of the HF power amplifier via a switch. The HF driver circuit can include a measurement device configured to measure a temperature of the HF power amplifier and a compensation device configured to control the bias voltage generator according to the temperature. The bias voltage generator is configured to provide a bias voltage to the HF power amplifier. By switching in the bias voltage, the HF power amplifier can be adjusted to a low quiescent current. By switching off the bias voltage, the HF power amplifier can be very rapidly and effectively blocked. As a result, very rapid switching-on and switching-off times, e.g., in a range of 10 to 50 ns, can be achieved.

A radio frequency (RF) summer circuit having a characteristic impedance Z.sub.0 comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z.sub.0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented. The RF summer circuit develops a summed signal at the third port equal to a sum of signals at the first and second ports modified by one of first and second gain values.

Dynamic automatic gain controller configuration in multiple input and multiple output receivers is provided by monitoring a given section of wireless spectrum for higher-priority signals using a first antenna set associated with a first Automatic Gain Controller (AGC) set while concurrently monitoring the given section of wireless spectrum for wireless packet-based traffic using a second antenna set associated with a second AGC set; in response to detecting a packet via the second antenna set: re-associating the first antenna set and the second antenna set to a third AGC set; receiving the packet via the first antenna set and the second antenna set using the third AGC set; and in response to the packet being received, re-associating the first antenna set to the first AGC set and the second antenna set to the second AGC set.

A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.

A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.

A power detector device includes a power detector circuit, a filter circuit, and a calibration circuitry. The power detector circuit is configured to detect a first signal to generate a second signal. The filter circuit is configured to filter the second signal to generate a third signal. The calibration circuitry is configured to determine first signal strength information in response to the third signal, adjust a gain of the power detector circuit to obtain second signal strength information, and combine the first signal strength information and the second signal strength information, in order to calibrate a detection power range of the power detector circuit to be linear.