The present invention discloses a transmission circuit having output power compensation mechanism. A base-band circuit receives and processes a digital input signal to perform conversion and amplification according to at least one gain parameter to generate an analog output signal. A frequency up-converting circuit performs frequency up-conversion on the analog output signal to generate an RF signal. A RF amplification circuit amplifies the RF signal to generate an output RF signal to an antenna. A temperature monitoring circuit monitors temperature of the RF amplification circuit to generate an instant temperature value thereof. A calibration circuit increases at least a part of the gain parameter when the instant temperature value makes a power of the RF amplification circuit decrease and decreases at least a part of the gain parameter when the instant temperature value makes the power increase.

A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

A receiver (100) with an antenna array (150) provides interference reduction for blocking signals received by the receiver (100) by controlling different receiver blocks (110) associated with different antenna elements (112) of the array (150) differently, particularly for those antenna elements (112) in the corner or proximate a corner or edge of the array (150), responsive to a power level of a combined signal resulting from all antenna elements (112). As a result, the solution presented herein enables a receiver (100) to more accurately target the gain control such that the antenna elements (112) and associated receiver circuitry (110) most likely to be impacted by unwanted signals have a reduced gain, while the antenna elements (112) and associated receiver circuitry (110) less likely to be impacted by unwanted signals can operate with a higher gain.

A receiving system includes a controller that selectively activates one or more of a plurality of paths between an input of a first multiplexer and an output of a second multiplexer. The receiving system includes a plurality of bandpass filters, each one of the bandpass filters being disposed along a corresponding one of the plurality of paths and configured to filter a signal received at the bandpass filter to a respective frequency band. The receiving system also includes a plurality of variable-gain amplifiers (VGAs), each one of the plurality of VGAs disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the VGA with a gain controlled by an amplifier control signal received from the controller. At least one, but not all, of the VGAs is a fixed-gain amplifier with a bypass switch to selectively bypass the fixed-gain amplifier.

An apparatus includes a radio-frequency (RF) receiver, which includes an automatic gain-control (AGC) circuit to use a gain signal to set a gain of front-end circuitry of the RF receiver. The RF receiver further includes an interference-detection circuit to use a value of the gain signal to detect an interference signal.

An integrated circuit device is provided. In some examples, the integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response. A main path is coupled to the amplifier stage that receives the amplified signal and provides a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path also receives the amplified signal and provides a second feedback signal corresponding to a signal strength of the data-bearing portion and an interference component. A gain control circuit is coupled to the main path and the control path that receives the first and second feedback signals and provides the control signal in response to the feedback signals. In some such examples, the control path and main path include separate mixer stages with different performance characteristics.

An electronic device comprises a first communication circuit configured to transmit at least one radio frequency (RF) signal, at least one antenna structure, electrically coupled to the first communication circuit, and including a plurality of antenna elements, at least one processor operatively coupled to the first communication circuit, and memory operatively coupled to the at least one processor. The memory stores instructions that, when executed by the at least one processor, causes the processor to perform a plurality of operation. The plurality of operations comprises identifying mobility information of the electronic device, identifying a beam width of a beam formed by at least a part of the plurality of antenna elements based on at least part of the mobility information of the electronic device, the beam being used to search for or communicate with an external electronic device, and forming the beam having the identified beam width.

Methods, systems, and devices for wireless communications are described that provide a repeater for beamforming a received signal at a first radio frequency via one or more scan angles or beamforming directions and then retransmitting and beamforming the transmitted signal at the first radio frequency via one or more scan angles or beamforming directions. Repeaters may perform heterodyning or downconverting on the received signal to reduce a frequency of the signal from the first frequency to an intermediate frequency (IF), and then band-pass filter the IF signal around a desired center frequency. The repeater may then heterodyne or upconvert the filtered IF signal back to the first frequency for the retransmission of the signal.