Certain aspects of the present disclosure provide circuits for generating high accuracy millimeter wave or radio frequency (RF) wideband in-phase (I) and quadrature (Q) oscillating signals having acceptable amplitude and phase mismatch over process, voltage, and temperature (PVT) variations with reduced cost, area, and power consumption. In one example apparatus, a polyphase filter having a first stage and a second stage is provided. Each stage comprises resistive elements and capacitive elements. Certain aspects of the present disclosure provide for intentional resistive and/or capacitive value mismatch between the resistive or capacitive values of one or multiple stages such that the phase mismatch between the resulting I and Q signals may be reduced without degrading the amplitude mismatch. Certain aspects of the present disclosure provide for replacing the resistive elements in at least one stage with transistors operating in the triode region, where the on-resistance is controlled by a feedback network.

A calibration method and a tuning method for an on-chip differential active RC filter are provided. The calibration method comprises: obtaining zero-crossing time of a differential signal outputted by a single-pole point real number filter by analyzing the single-pole point real number filter; setting a reference clock period according to the relationship between the zero-crossing time and the bandwidth of the single-pole point real number filter, and setting a calibration working time sequence according to the reference clock period; and scanning an RC configuration of an RC array according to the calibration working time sequence to realize calibration of the RC array.

A second-order low-pass canonical filter designed for precise signal processing and a method for assembling and a method for low pass filtering a current signal are described. The filter comprises two main stages. The first stage includes a current source that feeds into a first programmable current division network (CDN), which is in series with a first current follower (CF) having a single output terminal. This arrangement is followed by a first three output terminal CF circuit. The second stage consists of a second CDN network connected in series with the negative output of the first three output terminal CF circuit. A second single output terminal CF in series with the second CDN.sub.2 is connected to a second three output terminal CF, whose negative output terminal provides a low pass filtered output current I.sub.0. This filter architecture is particularly advantageous for applications requiring stable and adjustable frequency filtering capabilities.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:

Mc/+Mr

Mr{square root over (1/2ft)}[Math. 1] where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, denotes a resistivity of the resistor, denotes a MOS capacitance rate of the MOS capacitor, and denotes a MOM capacitance rate of the MOM capacitor.

A second-order low-pass canonical filter designed for precise signal processing and a method for assembling and a method for low pass filtering a current signal are described. The filter comprises two main stages. The first stage includes a current source that feeds into a first programmable current division network (CDN), which is in series with a first current follower (CF) having a single output terminal. This arrangement is followed by a first three output terminal CF circuit. The second stage consists of a second CDN network connected in series with the negative output of the first three output terminal CF circuit. A second single output terminal CF in series with the second CDN.sub.2 is connected to a second three output terminal CF, whose negative output terminal provides a low pass filtered output current I.sub.0. This filter architecture is particularly advantageous for applications requiring stable and adjustable frequency filtering capabilities.

Filter circuitry is provided that includes a resistor having a first terminal coupled to an input of the filter circuitry and having a second terminal coupled to an output of the filter circuitry, a capacitor having a first terminal coupled to the second terminal of the resistor and having a second terminal coupled to a power supply line, and a transistor coupled to the first terminal of the resistor or the second terminal of the resistor. The transistor can be coupled to a bias current and additional capacitors. A switch can be coupled between the transistor and the first terminal of the resistor. A switch can be coupled between the transistor and the second terminal of the resistor. The filter circuitry can be configured to provide a low-pass filter response with a reduced in-band droop when the switch and the bias current are activated.

An oscillator has a feedback loop with a signal output, a multi-pole resonator, and a gain block. The gain block applies a gain sufficient to generate a stable oscillation signal at the signal output; and the multi-pole resonator is tunable between two or more resonance modes.