An FIR filter includes: an address signal generation unit configured to generate an address signal of an address value in accordance with k bit values that correspond to k filter coefficients having a symmetric property; and an extraction unit configured to extract a computation result that corresponds to the address value indicated by the address signal from the table, in which, in the table, a plurality of computation results in which sets of computation results indicating the same values among 2 to the power of k patterns of computation results which are obtained by adding up k results of multiplication, the k results of multiplication being results obtained by multiplying each of k filter coefficients having a symmetric property by each of k bit values that correspond to k filter coefficients are commonly shared, and the plurality of address values are associated with each other.

An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

In order to enhance the speed of a processing necessary for setting the factor of a filter and further maintain the accuracy of the filter, a digital processing apparatus includes: a Fourier transform unit that Fourier transforms a time domain digital signal, thereby generating N frequency domain signals; a filter unit that uses N first factors to process the frequency domain signals in the frequency domain; an inverse Fourier transform unit that transforms the frequency domain signals as processed by the filer unit to a time domain digital signal; a low accuracy factor calculation unit that uses m second factors to calculate N first A factors; a high accuracy factor calculation unit that includes a factor division unit for calculating respective ratios of N third factors to the N first A factors and that also includes a factor variable unit for calculating N first B factors varying stepwise from one to the respective ratios; a multiplication unit that multiplies the first A factors by the first B factors, thereby calculating the N first factors; and a control unit that controls the low accuracy factor calculation unit and high accuracy factor calculation unit by causing only the low accuracy factor calculation unit to operate with the first B factors being set to one and thereafter causing the high accuracy factor calculation unit to calculate the first B factors based on the third factors.

Systems, apparatuses, and methods for implementing a low power decimator. A decimator may receive a plurality of input samples from a digital microphone. The decimator may include one or more coefficient tables for storing values combining two or more filter coefficients for filtering the received samples. The decimator may utilize a concatenation of multiple samples to perform a lookup of a corresponding coefficient table. The coefficient tables may store only the necessary non-redundant values for all coefficient combinations which can be applied to the multiple samples. The result of the lookup of the coefficient table may have its sign inverted or be zeroed based on the values of the multiple samples.

Systems, apparatuses, and methods for implementing a low power decimator. A decimator may receive a plurality of input samples from a digital microphone. The decimator may include one or more coefficient tables for storing values combining two or more filter coefficients for filtering the received samples. The decimator may utilize a concatenation of multiple samples to perform a lookup of a corresponding coefficient table. The coefficient tables may store only the necessary non-redundant values for all coefficient combinations which can be applied to the multiple samples. The result of the lookup of the coefficient table may have its sign inverted or be zeroed based on the values of the multiple samples.

A receiver receives signals and noise over a frequency spectrum of a desired received signal. The desired received signal is spread using code division multiple access. The received signals and noise are demodulated to produce a demodulated signal. The demodulated signal is despread using a code uncorrelated with a code associated with the desired received signal. A power level of the despread demodulated signal is measured as an estimate of the noise level of the frequency spectrum.

An example system is configured to convert a first digital signal having a first sampling rate into a second digital signal having a second sampling rate that is different from the first sampling rate. The system includes an input circuit to receive the first digital signal at the first sampling rate; a fractional finite impulse response (FIR) circuit configured to shift the first digital signal by a value corresponding coefficients of the FIR circuit, with the value being based on an integer value or a non-integer value; memory to store the coefficients for the FIR circuit; and processing circuitry to receive information corresponding to the second sampling rate, to obtain the value based on the information, to obtain the coefficients from the memory based on the value, and to provide the coefficients to the FIR circuit.

An example system is configured to convert a first digital signal having a first sampling rate into a second digital signal having a second sampling rate that is different from the first sampling rate. The system includes an input circuit to receive the first digital signal at the first sampling rate; a fractional finite impulse response (FIR) circuit configured to shift the first digital signal by a value corresponding coefficients of the FIR circuit, with the value being based on an integer value or a non-integer value; memory to store the coefficients for the FIR circuit; and processing circuitry to receive information corresponding to the second sampling rate, to obtain the value based on the information, to obtain the coefficients from the memory based on the value, and to provide the coefficients to the FIR circuit.