In some aspects, an audio processor may provide, to each digital sample rate converters in a time division multiplexing (TDM) data chain, a set of TDM clocks that include a sample rate clock input and a bit clock input. The digital sample rate converters in each TDM data chain may connect to respective audio ports that each correspond to a stereo channel. The digital sample rate converters in each TDM data chain may receive digital audio inputs via the audio ports. The audio processor may receive, at one or more TDM inputs, a TDM audio stream from each of the one or more TDM data chains, wherein the TDM audio stream mixes the digital audio inputs based on the sample rate clock input and the bit clock input. Numerous other aspects are described.

Systems, methods, and other embodiments associated with converting an input signal into an output signal with a different sampling rate. In one embodiment, an apparatus includes a feedforward circuit configured to receive the input signal comprised of discrete data samples with the first sampling rate and to generate a first intermediate value based, at least in part, on a feedforward coefficient and the input signal. The apparatus includes a feedback circuit configured to generate a second intermediate value that is based, at least in part, on a feedback coefficient and a predetermined number of previous samples of the output signal. The apparatus includes a signal combiner configured to combine the first intermediate value and the second intermediate value together to interpolate a data sample of the output signal at the second sampling rate. The output signal is a converted form of the input signal at the second sampling rate.

A system for processing audio data includes an isochronous data interface to output a first stream of audio data, a plurality of output sample rate converters to output a second stream of audio data, a plurality of transaction control registers to control routing of the first stream of audio data between the isochronous data interface and an output sample rate converter of the plurality of output sample rate converters, a processor to remove first header data from the first stream of audio data output from the isochronous data interface and to write the first header data to a circular buffer, a first audio header register to control forwarding of the first header data for prepending to the second stream of audio data output by the plurality of output sample rate converters, and a plurality of output control registers to control write enables of the plurality of output sample rate converters.

Aspects of this disclosure relate to an asynchronous sample rate converter (ASRC) comprising a signal input configured to receive an input signal having one or more input signal values at a first sample rate, a first clock input configured to receive an input clock signal corresponding to the first sample rate, a signal output configured to provide an output signal having one or more output signal values at a second sample rate, a second clock input configured to receive an output clock signal corresponding to the second sample rate, a zero-padding circuit configured to add a plurality of zero values following at least one of the one or more input signal values, and a filter configured to generate the output signal, the output signal having one or more output signal values based on the input signal.

Control unit for a transmission system, including: a sample rate converter, which is coupled to a digital-to-analog converting unit, wherein digital input data (data_in) are feedable to the sample rate converter; a PRBS generator, wherein an output signal (ss_div) of the PRBS generator is feedable to the sample rate converter and to a delay element, wherein an output signal (ss_div_del) of the delay element is feedable to a frequency synthesizer, wherein the frequency synthesizer is clockable by a reference clock (clk_ref) and wherein an output signal (clk_ss) of the frequency synthesizer is feedable to a clock input of the sample rate converter and to a clock input of the digital-to-analog converting unit.

A device for processing a digital signal includes a Farrow structure (14) that applies to the digital signal a time-varying sample rate conversion from the fixed sample rate to a time varying sampling. The digital signal sampled at the time varying sampling is a resulting signal. The Farrow structure (14) is controlled from a control variable. A spectral analysis means (15) performs a spectral analysis of the resulting signal to determine the frequency values of the resulting signal. A determining means (16) determines a sparseness parameter of the frequency values of the resulting signal. A controlling means (17) modifies the control variable according to the value of the sparseness parameter.