H03K3/02315

BUILT-IN SELF-TEST METHOD AND APPARATUS FOR SINGLE-PIN CRYSTAL OSCILLATORS

A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.

QUADRATURE PHASE RELAXATION OSCILLATOR USING FREQUENCY ERROR COMPENSATION LOOP
20190319611 · 2019-10-17 ·

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less insensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Microcontroller programmable system on a chip

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Microcontroller programmable system on a chip

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks on-the-fly, e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Method of monitoring clock and oscillator module thereof

An oscillator module used with a plurality of power sources includes an oscillator unit, a clock monitor unit (CMU), a software module and a digital calibration circuit. The oscillator unit generates a clock signal. The CMU is coupled to the oscillator unit, determines whether an amplitude of the clock signal exceeds a predetermined threshold, and outputs an alarm signal if the amplitude of the clock signal is lower than the predetermined threshold. The software module is coupled to the CMU, and receives the alarm signal to output a calibration signal. The digital calibration circuit is coupled to the oscillator and the software module, and outputs a control signal in response to the clock signal and the calibration signal, adjusting the plurality of power sources to modify the clock signal.

RELAXATION OSCILLATOR AND WIRELESS DEVICE INCLUDING RELAXATION OSCILLATOR
20180351538 · 2018-12-06 ·

Provided is a relaxation oscillator having an extremely small temperature deviation in oscillation frequency. A first current (I1) generated by a reference voltage source and a first resistor having a positive first-order temperature coefficient is supplied to a first variable capacitor (C1) for oscillation, and a second current (I2) generated by a reference voltage source and a second resistor having a negative first-order temperature coefficient is supplied to a second variable capacitor (C2) for oscillation. A product of a value of a ratio of a first current to a second current and a value of a ratio of a first-order temperature coefficient of the second resistor to a first-order temperature coefficient of the first resistor, and a value of a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor have the same absolute value and opposite signs.

Supply-noise-rejecting current source

Various technologies pertaining to a high-impedance current source are described herein. The current source outputs a substantially constant current by way of a first transistor that draws current from a supply. The current source is configured to feed back noise from the supply to a feedback resistor at an input of an operational amplifier (op-amp) by way of a second transistor. The feedback resistor and the op-amp are configured such that responsive to receiving the supply noise feedback, the op-amp drives a gate voltage of the first transistor to cause the first transistor to reject the supply noise and cause the output of the current source to remain substantially constant.

PSoC architecture

An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.

Hybrid pulse-width control circuit with process and offset calibration
10003328 · 2018-06-19 · ·

A hybrid pulse-width control circuit is provided that includes a ramp voltage generator for generating a ramp voltage signal. A clock pulse generator asserts an output clock signal responsive to the ramp voltage signal equaling a reference voltage.