A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

Disclosed in a PAM-4 receiver using pattern-based clock and data recovery circuitry, which includes an analog front end that receives an external signal and recovers channel loss to output a refined PAM-4 signal, a comparison unit that receives the PAM-4 signal and compares the PAM-4 signal with a reference voltage to generate a recovery signal, and a recovery unit that receives the recovery signal and recovers data and a clock. The analog front end includes an equalizer that matches amplitudes of all frequency components of the external signal and an amplifier that amplifies an output signal of the equalizer.

A pull-up voltage detection circuit is for use in a serial bus. The serial bus includes a communication signal. During a communication interval, the communication signal is toggled based on a pull-up voltage for communicating on the serial bus via open-drain scheme. The pull-up voltage detection circuit includes: at least one comparator circuit for comparing the communication signal or a divided voltage thereof with at least one reference voltage in a detection procedure, so as to generate at least one comparison result; and a selector circuit for selecting one of plural predetermined voltages according to the at least one comparison result. The selected predetermined voltage serves as a logic threshold voltage corresponding to the pull-up voltage. In the communication interval, the logic state of the communication signal is determined by comparing the communication signal and the logic threshold voltage for communicating on the serial bus.

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.