A ramp voltage signal generated by an equivalent series resistance compensation circuit in prior art is not linear, and average amplitude and maximum amplitude of the ramp voltage signal changes with an input voltage and a turn-on time. It results in a comparison result or compensation value generated by a comparator of the constant-frequency turn-on circuit will change accordingly and is difficult to control. Thus, it is difficult to design the stability of the system. The embodiments of the present disclosure design an equivalent series resistance compensation circuit including hardware circuits. Through functions of these hardware circuits, a ramp voltage signal of which average amplitude and a maximum amplitude are constant is generated, thereby solving problems encountered in the prior art.

A signal transmission device includes a first and a second circuit, in which the first circuit includes: a transmitter configured to generate a transmission signal according to an input signal; a first receiver configured to feed a first reception signal to a first logic circuit to generate a first single output signal; and at least one first isolating element arranged between the transmitter and the first receiver and configured to constitute a first signal transmission path for transmission of the transmission signal from the transmitter and output the first reception signal to the first receiver. The second circuit includes: a second receiver configured to generate a second single output signal; and a second isolating element arranged between the first logic circuit and the second receiver and configured to constitute a second signal transmission path, different from the first signal transmission path, for transmission of the transmission signal from the transmitter.

A comparator includes a differential input, an output, a pair of first transistors coupled to the differential input, a pair of second transistors coupled to the output, and a SET protection circuit. Gate terminals of the pair of first transistors are coupled to the differential input of the comparator. The second terminals of the pair of second transistors are coupled to the second terminals of the pair of first transistors. The SET protection circuit has a current source and a transistor. The transistor of the SET protection circuit has a first terminal coupled to the body terminals of the pair of first transistors to bias the body terminals of the pair of first transistors separate from the first terminals of the pair of first transistors. A gate terminal of the transistor of the SET protection circuit is coupled to a terminal of the differential input of the comparator.

A device includes a comparator circuit and a current generator circuit. The comparator circuit, responsive to a current, receives an input signal and a reference signal, compares the input signal with the reference signal, and generates an output signal that indicates the result of comparison. The current generator circuit includes a current mirror circuit and a current booster circuit. The current mirror circuit generates the current. The current booster circuit amplifies the current from an initial current value to a higher current value and maintains the current at the higher current value over a predetermined duration of time. A method for reducing a settling time of an output of the device is also disclosed.

Certain aspects are directed towards an interpolator and/or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.