To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

A driver IC (100) includes a pair of output terminals in each of a plurality of channels and in each of the channels, power is supplied from the pair of output terminals (OUT1 and OUT2, OUT3 and OUT4, OUT5 and OUT6 or OUT7 and OUT8) to a load (M1, M2, M3 or M4). In each of the channels, the pair of output terminals are adjacent to each other.

A switching regulator may be used to generate an output voltage from an input voltage. The switching regulator includes; an inductor including a first terminal and a second terminal that passes an inductor current from the first terminal to the second terminal, a first switch that applies the input voltage to the first terminal when turned ON, a second switch that applies a ground potential to the first terminal when turned ON, a feedback circuit configured to estimate a load receiving the output voltage, detect when the inductor current reaches an upper bound or a lower bound, and adjust the lower bound based on the estimated load, and a switch driver configured to control the first switch and the second switch, such that the inductor current is between the upper bound and the lower bound in response to at least one feedback signal provided by the feedback circuit.

A DC-DC converter includes an output terminal, a reference voltage source, an error amplifier, and a compensation circuit. The error amplifier is coupled to the output terminal and the reference voltage source. The error amplifier is configured to generate an error signal representative of a difference between a voltage at the output terminal and a reference voltage provided by the reference voltage source. The compensation circuit is coupled to the error amplifier. The compensation circuit includes a resistor, a capacitor, and a switch control circuit. The resistor is coupled to the error amplifier. The capacitor is coupled to the resistor. The switch control circuit is configured to modulate connection of the resistor to the capacitor based on a switching frequency of the DC-DC converter.

An embodiment provides a circuit of cyclic activation of an electronic function including a hysteresis comparator controlling the charge of a capacitive element powering the function.

In one example, an electronic system includes, a user interface comprising an input device, a first actuator and a second actuator, the first and second actuators dually actuated by the input device, and a controller, including a comparator, a programmable device, and executable instructions residing in non-transitory memory thereon to, receive first and second output signals from the first and second actuators, respectively, convert the first and second output signals to first and second real-time logic states at the comparator, input the first and second real-time logic states from the comparator to the programmable device, and determine a fault status of the first and second actuators based on the first and second logic states input to a state machine of the programmable device, wherein the first and second logic states input to the state machine include the real-time logic states and historical logic states stored at the controller.

Control circuitry for controlling a current through an inductor of a power converter, the control circuitry comprising: comparison circuitry configured to compare a measurement signal, indicative of a current through the inductor during a charging phase of the power converter, to a signal indicative of a target average current through the inductor for the charging phase and to output a comparison signal based on said comparison; detection circuitry configured to detect, based on the comparison signal, a crossing time indicative of a time at which the current through the inductor during the charging phase is equal to the target average current for the charging phase; and current control circuitry configured to control a current through the inductor during a subsequent charging phase based on the crossing time.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.