A method for controlling a stepper motor includes calculating a duty cycle of a current provided to the stepper motor and comparing a difference, between the calculated duty cycle and a base duty cycle of current provided to the stepper motor under a base load condition, to a reference duty cycle value. The method also includes adjusting a peak current level of the current provided to the stepper motor responsive to the comparison.

According to an embodiment, an overheat protection circuit includes a reference voltage generation circuit, a constant current source, a second voltage generation circuitry, an output current detection circuit, and a blocking controller. The output current detection circuit generates a third current by subtracting the second current from the first current, and decreases the second current based on the third current as an output current generated by an output circuitry increases, the third current being proportional to the output current. The blocking controller compares the first and second voltages with each other, and generates a blocking control signal to block generation of the output current when the first voltage is higher than the second voltage. An overheat detection temperature drops as the second voltage drops, and detection of the overheat detection temperature is hastened as the output current increases.

The technical solution proposed by the present disclosure is to use whether a voltage difference reaches a hysteresis voltage of a hysteresis comparator to efficiently update a charge of a capacitor and achieve lower power consumption. On the other hand, since the advanced voltage holding circuit is designed to consume lower power, the refresh time must be designed longer, which makes it impossible to do a large number of yield tests. Thus, the technical solution proposed by the present disclosure can greatly shorten the test time in conjunction with the relevant application circuit, and increase the testability and reliability of a voltage holding device.

A voltage detector includes a voltage division circuit which outputs a divided voltage based on an input voltage, a comparison circuit which compares the divided voltage and a reference voltage to output a detection signal and a release signal, and a voltage limiting circuit which limits the divided voltage to a preset voltage.

A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier.

Comparison circuit and delay cancellation method are provided. The circuit includes a control circuit, capacitors and a transconductance amplifier circuit, wherein the control unit is configured to receive an input signal and control the comparison circuit to be in different working stages; the capacitors are configured to store a DC offset voltage signal at an automatic zero calibration stage; store the input signal when the output signal is inverted at a measurement stage; and store an equivalent delay voltage signal at a delay sampling stage; the transconductance amplifier circuit is configured to store the DC offset voltage signal to the capacitors at the automatic zero calibration stage; compare voltage signals on positive and negative input terminals and generate an output signal at the measurement stage; and store the equivalent delay voltage signal to the capacitors at the delay sampling stage. An inherent delay of the comparison circuit may be cancelled.

The present application relates to a hysteresis comparator, which comprises a hysteresis comparator circuit and a hysteresis generating circuit. The hysteresis comparator circuit two comparator legs each with a differential transistor and a load transistor. The differential transistors receive a comparator biasing current, which is variably divided based on the relative levels of the voltage signals applied to control terminals of the differential transistors. An output stage is provided for developing an output voltage signal based on currents flowing through the load transistors. The hysteresis generating circuit is arranged for selectively injecting a hysteresis current in or selectively drawing a hysteresis current from either one of the two comparator legs depending on the level of the output voltage signal.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

A voltage comparator (1) has a high switching speed and simplicity of design. It minimizes pulse-width distortion of input digital signals when functioning as a digital input buffer in high speed communications applications. In addition it provides a simple hysteresis circuit (31) that is easily tuneable with a reference current. The hysteresis circuit (31) is dependent on a reference current. This current may be chosen to have a proportionality to temperature, supply, or another selectable parameter, and may be programmable, in order to create the desired hysteresis performance.

A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.