A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.

A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.

The disclosure provides a universal oscillator. The oscillator includes an amplifier array. The amplifier array includes one or more amplifiers. A control logic unit is coupled to the amplifier array and activates the one or more amplifiers. A self-clock generating circuit is coupled to the control logic unit and generates a fixed clock. A counter receives the fixed clock from the self-clock generating circuit and provides a controlled clock to the control logic unit.

Provided is an electronic device includes an oscillator circuit that outputs a clock signal of predetermined frequency, a clock circuit that counts date and time in accordance with input of the clock signal, a temperature sensor that measures a temperature relating to a change of the predetermined frequency, a receiver that receives a radio wave from a positioning satellite, and a first processor and/or a second processor. The first processor and/or the second processor estimates an amount of time count difference in date and time counted by the clock circuit on the basis of a history of temperatures measured by the temperature sensor, and combines date and time counted by the clock circuit, the estimated amount of time count difference, and part of date-and-time information obtained from a radio wave received by the receiver to identify current date and time.

A method for operating a fast start-up oscillator system, which includes a reference oscillator and a quartz oscillator connected to an electronic oscillator circuit, which is provided to supply a master clock signal to a start-up controller configured to perform a fast start-up procedure of the quartz oscillator via the reference oscillator. The start-up controller includes a calculation unit and a memory unit for storing data in connection with the reference oscillator for starting the quartz oscillator. The method includes parameterising the calculation unit for starting the quartz oscillator, generating excitation bursts, determining a phase deviation in different successive periods between the oscillation of the reference oscillator and the oscillation of the quartz oscillator, calculating a frequency error in the calculation unit, and correcting the frequency of the reference oscillator to the frequency of the quartz oscillator.

A circuit device includes an oscillation circuit, a clock signal output circuit that outputs a clock signal based on an output signal from the oscillation circuit, and an output control circuit. The output control circuit includes a counter circuit that performs a counting process on the basis of the output signal from the oscillation circuit, and a count enable signal generation circuit that outputs a count enable signal for the counter circuit. The counter circuit starts the counting process when the count enable signal becomes active, and outputs an output enable signal for the clock signal to the clock signal output circuit on the basis of a result of the counting process.

A low power oscillator circuit with temperature compensation is illustrated. A current supply unit of an oscillator used to output an output current which is proportional to a reference current. As the temperature is increased, both a first threshold and the reference current of a unidirectional conduct in the temperature compensation circuit are decreased. Because a delay time of the oscillating signal is proportional to the first threshold voltage, and the delay time is inversely proportional to the reference current, the effects of the first threshold voltage and the reference current on the delay time are canceled, and the delay time of the oscillating signal is not affected by the temperature.

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

A parasitic capacitance mitigation circuit for a relaxation oscillator. The parasitic capacitance mitigation circuit includes a first switch coupled across a parasitic capacitance of a resistive sensing element and a second switch coupled between the parasitic capacitance and a reference voltage node. The parasitic capacitance mitigation circuit includes a pulse generator configured to: monitor a voltage across the parasitic capacitance; detect a voltage transient across the parasitic capacitance; and generate a pulse control signal in response to detecting the voltage transient. In response to the pulse control signal, the first switch opens and the second switch closes to discharge the parasitic capacitance through the second switch.

A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.