A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.

An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.

A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes power supply monitors across a die of the integrated circuit. A power supply monitor receives a power supply voltage and generates a code indicating a value of the power supply voltage. A first ring oscillator receives the power supply voltage and a pulse used as an enable signal. A pulse generator of the power supply monitor takes into account the process, voltage and temperature (PVT) characteristics of the integrated circuit by including at least a second ring oscillator and a modulus counter that receives an output of the second ring oscillator. Therefore, the pulse generated by the pulse generator is PVT dependent and increases gain of the power supply monitor.

A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.

An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

Provided are a transmission line module for a rotary traveling wave oscillator (RTWO) and a design method thereof. The transmission line module includes a substrate. The upper surface of the substrate is provided with a grounding metal layer, that is, a metal ground. The metal ground is provided with a rectangular groove. The rectangular groove penetrates front and rear sides of the metal ground along a length direction of the rectangular groove. The thickness of the rectangular groove is the same as the thickness of the metal ground. The rectangular groove is filled with a silicon dielectric plate that has the same shape and size as the rectangular groove. The upper surface of the silicon dielectric plate is provided with two parallel transmission lines along the length direction of the rectangular groove.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

A ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage.

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.