A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

A semiconductor device includes a plurality of cell rows, a first functional block and a second functional block. The plurality of cell rows at least includes a first cell row and a second cell row. The first functional block is formed in the first cell row and configured to provide a first predetermined function. The second functional block is formed in the second cell row and configured to provide a second predetermined function which is the same as the first predetermined function. The first cell row and the second cell row have at least one different physical property.

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.

A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.

According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth inverters, a third power supply supplying power to the second transfer gate, first and second signals having opposite logic levels for controlling the first transfer gate. The third power supply is significantly lower than the first or second power supply. The leakage current of the receiver is significantly reduced in the core when the second power supply remains on but the first power supply is turned off while the performance of the receiver remains the same.