A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

Methods, systems, and computer readable media described herein can be operable to facilitate transitioning a device from a first state to a second state. A switch described herein allows for the use of an electronic circuit to perform the toggle and persistence functions while simultaneously giving more flexibility to the industrial design and physical switch implementation. The switch allows this preserving of the state using only a toggle on a voltage and thus allowing for a hardware only solution. The switch described herein allows for the use of smaller and less complicated mechanical switches allowing for more compact industrial designs. The switch uses a programmable voltage reference as a 1 bit non-volatile memory cell that is programmed by means of a logic pulse to the device. This allows a software independent setting of the state of the privacy switch. This state will remain through power cycles.

Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.

A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.

A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).

The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.

A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.