A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.

Provided are a data signal detection device, and mobile industry processor interface radio frequency front-end device and system. The device includes: a first acquisition circuit, a second acquisition circuit and a selection output circuit. A first input terminal of the first acquisition circuit is connected to a second input terminal of the second acquisition circuit, and a second input terminal of the first acquisition circuit is connected to a first input terminal of the second acquisition circuit. Output terminals of the first acquisition circuit and the second acquisition circuit are connected to two input terminals of the selection output circuit. The acquisition circuit is configured to verify whether an acquisition signal meets a characteristic of a data signal; and the selection output circuit selects an acquisition signal from a received acquisition signal and a received invalid signal for output.

A multi-bit flip-flop (MBFF) has flip-flops connected to form an internal scan chain. One of the flip-flops outputs a first data-out signal at a first data output terminal of the MBFF, and includes a selection circuit, a latch-based circuit, and a data-out stage circuit. The selection circuit transmits a data signal or a test signal to an output node of the selection circuit to serve as an input signal. The latch-based circuit generates a first signal according to the input signal. The data-out stage circuit receives the first signal, and generates the data-out signal according to the first signal. When the MBFF operates in a test mode, the selection circuit transmits the test signal to serve as the input signal, and the data-out stage circuit keeps the data-out signal at a fixed voltage level regardless of a voltage level of the test signal.

Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

A bit data shifter receives an input signal and a plurality of clock signals. The bit data shifter includes a plurality of data shifter groups cascaded in sequence, and each of the plurality of data shifter groups cascaded in sequence includes a plurality of data latches cascaded in sequence and a master-slave flip-flop. The plurality of data latches cascaded in sequence is configured to delay the input signal in sequence based on the plurality of clock signals to generate a plurality of delayed signals. The master-slave flip-flop is configured to delay one of the plurality of delayed signals based on one of the plurality of clock signals to generate an input signal of a next data shifter group.

A master latch includes a latch input node and a latch output node, a first inverter with an input and an output, the input coupled to the latch input node and the output coupled to the latch output node, and a second inverter with an input and an output, the input coupled to the latch output node and the output coupled to the latch input node. The master latch further includes a first pull-up device connected between a source voltage and the latch input node, the first pull-up device configured to pull the latch input node up towards the source voltage when the latch output node is low, and a first pull-down device connected between the latch input node and a ground voltage, the first pull-down device configured to pull the latch input node towards the ground voltage when the latch output node is high.

A time to digital converter includes a polarity detecting module and a time digital conversion module. The time digital conversion module includes a digital coding unit, a ring vibration enabling unit, multistage differential time delay units sequentially forming a closed loop in series and a plurality of trigger units. Each differential time delay unit includes a first input end, a second input end, a first output end and a second output end. The first output end and the second output end of each differential time delay unit outputs differential signals which are complementary to each other. Mismatching between the ascending and descending time of a phase inverter and sampling of a trigger can be improved to enable signals entering the trigger units to be phase-complementary signals, thus improving the linearity of digital conversion.

A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

To provide a miniaturized data holding circuit. First and second MOS transistors respectively transmit a data signal and an inverted data signal to inputs of first and second inverting gates that constitute a state holding circuit when a clock signal is at a first level. Fifth and sixth MOS transistors are respectively inserted in a feedback path from an output of the second inverting gate to the input of the first inverting gate and a feedback path from an output of the first inverting gate to the input of the second inverting gate, and respectively transmit the outputs of the second and first inverting gates when the clock signal is at a second signal level. Seventh and eighth MOS transistors are constituted in a channel of a conductive type different from the first MOS transistor and connected in parallel to the fifth and sixth MOS transistors, respectively, and transmit the output of the second inverting gate and the output of the first inverting gate on the basis of the inverted data signal and the data signal, respectively.

A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.