The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

Devices and methods for generating an internal reset signal are explained. A first circuit (11) generates a first reset signal (r1), and a second circuit (12) generates a second reset signal (r2). The first reset signal (r1) and the second reset signal (r2) are linked to form a reset signal (r) with which a further circuit part (14) can be reset.

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

A circuit and method for reducing metastability of a CMOS SR flip flop is provided. The circuit comprises a first switching module and a second switching module that are operatively coupled to a first and second output terminal of the CMOS SR flip-flop. The method includes injecting current onto the first and second output terminals of the CMOS SR flip-flop at mutually opposite directions during permissible mid-range voltages of the output terminals. Further, the method includes driving the output terminals of the CMOS SR flip-flop into the predetermined state of zero and predetermined stable state of Vdd by utilizing the currents injected onto the output terminals. As a result, the metastable point of the CMOS flip-flop is diverted from the corresponding metastable voltage and thereby reduces the metastability of the CMOS SR flip-flop.

A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.

Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10.sup.19 (atoms/cm.sup.3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Integrated circuits having flip-flops with asynchronous reset capabilities are provided. The flip-flops may be single event upset (SEU) hardened registers implemented using dual-interlocked cell (DICE) latch circuits. A logic gate may be inserted at the data input of each flip-flop. A multiplexer may be inserted at the input of the clock tree that is being used to feed clock signals to each of the flip-flops. Both the logic gate and the multiplexer may receive an asynchronous reset signal. The multiplexer may also receive a normal clock signal and a delayed clock pulse signal that is triggered in response to detecting assertion of the reset signal.

A timing prediction circuit and method which relate to the field of circuit technologies and may be used to predict a timing margin of a to-be-predicted digital circuit, which are used to resolve a problem that a large quantity of devices are used to predict a probability that a timing error occurs in a to-be-predicted digital circuit. The timing prediction circuit includes a combinational logic circuit, a delay circuit, a sampling circuit, and a control circuit, where the sampling circuit includes N samplers, and an input end of each sampler is separately connected to an output end of the combinational logic circuit using the delay circuit, and an output end of each sampler is connected to an input end of the control circuit, where N is an integer equal, and N≧2. The present invention can be used to predict a timing margin of a to-be-predicted digital circuit.

A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.