Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a Zener diode, a first current source, a first n-type field effect transistor (FET), a first inverter circuit, and a second current source. The Zener diode has a cathode coupled to a first node and an anode coupled to a second node. The first current source has a first terminal coupled to the second node and a second terminal coupled to a ground terminal. The first n-type FET has a gate terminal coupled to the second node, a source terminal coupled to the ground terminal, and a drain terminal coupled to a third node. The first inverter circuit has an input coupled to the third node and an output coupled to a fourth node. The second current source has a first terminal coupled to a fifth node and a second terminal coupled to the third node.

An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.

A flag holding circuit includes: a flag setting part connected to a voltage supply line and charging a capacitor according to an input signal; a flag determination part outputting an output signal based on a charging voltage of the capacitor; and a discharging part discharging the capacitor. The flag setting part includes: a switch having a first terminal connected to a connection line between the flag determination part and the discharging part and a second terminal connected to the voltage supply line or a grounding line according to a signal level of the input signal, and connecting or disconnecting the voltage supply line or the grounding line with the connection line according to a leakage control signal; and a switch control part, generating the leakage control signal whose signal level changes to be greater than a power supply voltage according to a clock signal and supplying it to the switch.

A flag retaining circuit comprises a first capacitor element having one end connected to a first line and the other end grounded; a flag setting unit that charges the first capacitor element according to an input signal; a flag checking unit that outputs 0 or 1 based on the potential of the first capacitor element; and a discharging unit that discharges the first capacitor element. The discharging unit includes a transconductance element that discharges the first capacitor element via the first line; a control switch that receives supply of the voltage on a second line; and a second capacitor element having one end connected to a node between a control input end of the transconductance element and the control switch, and the other end grounded. The flag checking unit outputs the inverse of the voltage on the first line onto the second line.

An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.

A power-on reset circuit supplies a reset pulse to a sequential circuit to be initialized. A latch circuit includes a first inversion circuit and a second inversion circuit structured to invert and amplify a signal input thereto, with an output node of the first inversion circuit connected to an input node of the second inversion circuit, and with an output node of the second inversion circuit connected to an input node of the first inversion circuit. A decision circuit receives the first signal from the output node of the first inversion circuit and the second signal from the output node of the second inversion circuit and generates a reset pulse on the basis of the first signal and the second signal.

The present application relates to a hysteresis comparator, which comprises a hysteresis comparator circuit and a hysteresis generating circuit. The hysteresis comparator circuit two comparator legs each with a differential transistor and a load transistor. The differential transistors receive a comparator biasing current, which is variably divided based on the relative levels of the voltage signals applied to control terminals of the differential transistors. An output stage is provided for developing an output voltage signal based on currents flowing through the load transistors. The hysteresis generating circuit is arranged for selectively injecting a hysteresis current in or selectively drawing a hysteresis current from either one of the two comparator legs depending on the level of the output voltage signal.

A control system for a machine having at least one control element is disclosed. The control system includes multiple input sensors in communication with the control element. The input sensor generates an input signal based on an input to the control element. The control system includes multiple actuating members to control operations of the machine. The control system includes a controller in communication with the input sensors and the actuating members. The controller receives the input signal from the input sensor and determines an imposed hysteresis level corresponding to the input signal based on a hysteresis input function. The controller is further configured to generate a hysteresis conditioned input signal based on the imposed hysteresis level.