A circuit includes a first pair of transistors coupled in series between a supply voltage node and an output node and a second pair of transistors coupled in series between the output node and a ground node. The circuit further includes a first diode-connected transistor coupled between a first node between the first pair of transistors and the output node, and a second diode-connected transistor coupled between a second node between the second pair of transistors and the output node.

A crystal oscillation circuit includes a crystal oscillator coupled between an input pad node and an output pad node, a current mirror inverting amplifier configured to have a first input terminal coupled to the input pad node and an output terminal coupled to the output pad node, a detection logic circuit configured to detect a signal of the output pad node to generate an output pad node detection signal, and an automatic control logic circuit configured to apply a pull-up driver control signal to a second input terminal of the current mirror inverting amplifier in response to the output pad node detection signal. The current mirror inverting amplifier operates with a first gain or a second gain lower than the first gain according to the pull-up driver control signal.

An omnipolar magnetic sensor system includes an input stage and a behavior component. The input stage is configured to receive a source signal and to selectively chop the source signal. Further, the input stage is configured to balance the source signal using behavior parameters and generate a balanced source signal.

A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

The present invention provides an electronic circuit for controlling an actuator comprising a transceiver unit (1) for a bus system the bus terminal (2) of which has a monostable behavior with an active period of greater than 1 ms, wherein the transceiver unit (1) is controlled by a microcontroller (3), wherein the monostable behavior of the transceiver unit (1) is switched off with additionally superimposed control pulses, wherein the time interval between two control pulses is smaller than the monostable active period of the transceiver unit (1) and the control pulses are generated by temporal combination of two control signals the time resolution of which is lower than the pulse duration of the control pulses derived therefrom, which is implemented by use of a RC combination (4) and/or a logic gate (6) with a differentiating or delaying effect.

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

The present application relates to a hysteresis comparator, which comprises a hysteresis comparator circuit and a hysteresis generating circuit. The hysteresis comparator circuit two comparator legs each with a differential transistor and a load transistor. The differential transistors receive a comparator biasing current, which is variably divided based on the relative levels of the voltage signals applied to control terminals of the differential transistors. An output stage is provided for developing an output voltage signal based on currents flowing through the load transistors. The hysteresis generating circuit is arranged for selectively injecting a hysteresis current in or selectively drawing a hysteresis current from either one of the two comparator legs depending on the level of the output voltage signal.

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

According to embodiments of the present invention, an oscillator is provided. The oscillator includes a switched capacitor circuit arrangement configured to generate a predetermined voltage, a transconductance-capacitor filter configured to receive the predetermined voltage and a reference voltage, and to generate an output filter voltage based on a differential result between the predetermined voltage and the reference voltage, wherein a value of the output filter voltage is variable in response to the differential result, and a period control circuit arrangement configured to receive the output filter voltage, and further configured to generate an oscillator signal, wherein a period of the oscillator signal is variable in response to the value of the output filter voltage, wherein the oscillator is configured to control the switched capacitor circuit arrangement based on the oscillator signal to generate the predetermined voltage to be matched to the reference voltage.

A device includes a general-purpose input/output node, a serial identifier register, and serial identifier reassignment circuitry. The serial identifier register stores a serial identifier associated with the device. The serial identifier reassignment circuitry is coupled to the general-purpose input/output node and the serial identifier register. The serial identifier reassignment circuitry sets a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node. By setting a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node, the serial identifier may be easily changed using a pull-up or pull-down resistor external to the device.