In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

A semiconductor circuit according to the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that includes a gate, a drain, and a source, and is configured to store a threshold state; a second transistor that couples the first node to a first terminal by being turned on; a third transistor that couples a first predetermined node to the gate of the first transistor; and a driving section that controls operations of the second transistor and the third transistor, and applies a control voltage to a second terminal. The first terminal is one of the drain or the source of the first transistor. The first predetermined node is one of the first node or the second node. The second terminal is another of the drain or the source of the first transistor.

Apparatus for generating high pulse voltage comprises a high DC voltage source, a low DC voltage source, an inductive load, two controllable gates, a controllable switch and, connected in series, a capacitor, a booster diode and an additional controllable switch, as well as a controllable pulse duration converter for pulses from a rectangular pulse generator. The preceding connection of the booster diode anode with the negative terminal of the low DC voltage source ensured by the pulse duration converter and second controllable switch correlates the booster diode switching time with the moment of closing the both controllable gates. Thus, the pulse noise present in the prior art designs is eliminated, and the level of interference emitted into the surroundings is decreased.

A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a fourth region with the first region and the second region provided therebetween, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, and a second conductor over the second region with the third insulator provided therebetween. A part of the third insulator is positioned between the second conductor and the side surface of the second insulator.

A voltage clamping circuit includes a first detection circuit, a second detection circuit, and a discharge circuit. The first detection circuit detects a voltage level of a power voltage during a first operation period of a semiconductor apparatus. The second detection circuit detects the voltage level of the power voltage during a second operation period of the semiconductor apparatus. The discharge circuit changes the voltage level of the power voltage based on the detection results of the first and second detection circuits.

A power-on reset (POR) circuit includes: a signal generator circuit for generating a first and a second signal according to an input voltage, and a comparator circuit. The comparator circuit, having a non-zero input offset, includes a first MOS transistor with a first conductive type and having a first conductive type gate and a first threshold voltage, and a second MOS transistor with a first conductive type and having a second conductive type gate and a second threshold voltage. The input offset relates to a difference between the first and the second threshold voltage. The first and the second signal control the first and the second MOS transistors respectively to generate a POR signal. When the input voltage exceeds a POR threshold which relates to a predetermined multiple or ratio of the input offset, the POR signal transits its state.

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.

Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.