Disclosed is a high speed level shifter which converts a low voltage into a high voltage. The high speed level shifter includes an output circuit configured to output an output signal of a high voltage range in response to an input signal of a low voltage range; an input circuit operated in the low voltage range, and configured to control output of the output signal through an output terminal in response to the input signal; and a connection circuit configured to drop a voltage applied to the input circuit from the output circuit.

An ion trap apparatus (e.g., ion trap chip) having a plurality of electrodes is provided. The ion trap apparatus may comprise a plurality of interconnect layers, a substrate, and at least one integrated switching network layer disposed between the plurality of interconnect layers and the substrate. The integrated switching network layer may comprise a plurality of monolithically-integrated controls and/or switches configured to condition a voltage signal applied to at least one of the plurality of electrodes. An example ion trap apparatus may comprise a surface ion trap chip. The ion trap apparatus may be configured to operate within a cryogenic chamber.

An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.

In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source.

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

Disclosed is an output buffer circuit for a display driving apparatus, which generates an output voltage by using a bias current controlled by digital-to-analog conversion for interpolation data, the output buffer circuit including a decoder configured to output control data obtained by decoding interpolation data, and an output circuit configured to output an output voltage by using a bias current having the amount of current controlled by digital-to-analog conversion for the control data.

An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vol+ and Vol−; and an output alignment circuit configured to output voltages Vo+ and Vo− that are triggered by an edge of a combination of Vol+ and Vol−, and where Vo+ and Vo− are set by high states of Vol+ and Vol− prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vol+ and Vol−; and outputting, by an output alignment circuit, voltages Vo+ and Vo− that are triggered by an edge of a combination of Vol+ and Vol−, and where Vo+ and Vo− are set by high states of Vol+ and Vol− prior to a transition on an input of the level-shifter circuit.

A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.