A bi-directional level shift circuit shifts signal levels between a first signal line and a second signal line. The circuit includes a first transistor and a second transistor. The first transistor includes a first gate connected to the second signal line, a first source connected to the first signal line, and a first drain connected to a voltage rail which supplies voltage. The second transistor includes a second gate connected to the voltage rail, a second source connected to the first signal line, and a second drain connected to the second signal line.

Certain aspects of the present disclosure are directed to a regulator. The regulator generally includes a source follower circuit and a low-voltage assist circuit. The low-voltage assist circuit generally includes a first transistor having a gate coupled to an output node of the source follower circuit, a voltage comparison circuit having a first input coupled to a source of the first transistor and a second input coupled to a control input node of the source follower circuit, and a second transistor having a gate coupled to an output of the voltage comparison circuit and a drain coupled to the output node of the source follower circuit.

A half bridge circuit is disclosed. The half bridge circuit includes a low side transistor having a low side transistor gate, where a low side transistor gate voltage at the low side transistor gate is controlled by a low side gate signal. The half bridge circuit also includes a high side transistor having a high side transistor gate, where a high side transistor gate voltage at the high side transistor gate is controlled by a high side gate signal. The half bridge circuit also includes a semiconductor circuit configured to allow current to flow from a ground referenced power supply node to a first floating power supply terminal. The semiconductor circuit includes a first transistor, where a gate voltage is controlled by a gate drive circuit control signal, a source is connected to the ground referenced power supply node, and a drain connected to the first floating power supply terminal.

An imaging device for improving the determining speed of a comparator and reducing power consumption. The comparator imaging device includes a differential input circuit that operates with a first power supply voltage, the differential input circuit outputs a signal when an input signal is higher than a reference signal in voltage, and a positive feedback circuit that operates with a second power supply voltage lower than the first power supply voltage. The positive feedback circuit accelerates transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit. The imaging device further includes a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.

A power supply comprising a first-stage capacitor configured to provide energy to a second stage power converter. An energy transfer element coupled to the first-stage capacitor. A reservoir capacitor coupled to the energy transfer element. The reservoir capacitor is configured to receive charge from the energy transfer element. A power switch configured to control a transfer of energy from an input of the power supply to the first-stage capacitor. A controller coupled to the power switch, the controller configured to generate a hold-up signal in response to the input of the power supply falling below a threshold voltage. A charge circuit comprising a first switch and a second switch configured to be controlled by the hold-up signal. The first switch couples the reservoir capacitor to an input of the energy transfer element. The second switch is configured to uncouple the reservoir capacitor from receiving charge from the energy transfer element.

A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage V.sub.ON and the turn-off voltage V.sub.D to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.

A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.

Provided is a circuit device including: a first terminal electrically coupled to one end of a vibrator; a second terminal electrically coupled to the other end of the vibrator; an oscillation circuit electrically coupled to the first terminal and the second terminal, and oscillating the vibrator; a third terminal to which an external input signal is input; a switch circuit provided between a first wiring which couples the first terminal and the oscillation circuit with each other and the third terminal, and having a P-type transistor; and a control circuit outputting a regulated voltage, in which a power supply voltage is regulated, as a substrate voltage of the P-type transistor.

Systems, methods, and devices for generation of narrow pulses in a flying high-voltage domain that are used as a timing control signal are presented. A main signal processing path that generates the timing control signal is replicated and used to detect time and duration of perturbations due to flying events in the main signal processing path based on a fixed input level to the replicated path. Detected time and duration of the perturbations are used to generate a blanking control signal to the main signal processing path. According to one aspect, the main signal processing path may be part of a high side level shifter that operates in a flying high-voltage domain and used to control a high-voltage switching device.